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Using poly-Si gate MOS capacitors, the tunnel oxide degradation due to high electric field stress is shown to be accelerated by the oxidation of the Si/sub 3/N/sub 4/ film in inter-poly ONO films and by high-temperature annealing. Microscopic Raman spectroscopy confirms that increased tensile stress in poly-Si gates leads to tunnel oxide degradation, Therefore, using CVD-SiO/sub 2/ film as the top...
The gate electrode polycrystalline silicon (gate poly-Si)/gate insulator SiO/sub 2/ interface structure has been studied for obtaining reliable nonvolatile memory devices. The voltage deviation of Fowler-Nordheim tunneling current of the devices is discussed in terms of the SiO/sub 2/ surface roughness. High resolution scanning electron microscope (SEM) and atomic force microscope (AFM) measurements...
An internal erase and erase-verify control system implemented in all electrically erasable, reprogrammable, 80-ns, 1-Mb flash memory suitable for in-system reprogram applications is discussed. This system features a command signal latch, a sequence controller, and a verify voltage generator. Timing in the electrical erase mode is shown. The erase mode is initiated by a 50-ns pulse. An erase and erase-verify...
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