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This paper presents a decoupling capacitance boosting method for on-chip resonant supply noise reduction for DVS systems. The switching controls of decoupling capacitors depending on the supply noise states achieve an effective noise reduction and fast settling time simultaneously compared with the conventional passive decoupling capacitors. The measurement results of a test chip fabricated in a 0...
The unstable/unpredictable LSI operation caused by the PVT (Process Voltage Parameter) variations, along with the aging effect such as NBTI/PBTI, is one of the serious issues in current and future scaled LSIs. In these situations, where operation environments in the field are hard to predict at the stages of circuit design and test, the conventional approach of the margin-based design and test in...
We introduce a 42x cascaded time difference amplifier (TDA) using differencial logic delay cells with 0.18??m CMOS process. By employing differential logic cells for the delay chain instead of CMOS logic cells, our TDA has stable time difference gain (TD gain) and fine time resolution. Measurement results show that our TDA achieves less than 5.5% TD gain offset and ??250ps input range.
Extremely high density CMOS technology for 40 nm low power applications is demonstrated. More than 50% power reduction is achieved as a SoC chip by aggressive shrinkage and low voltage operation of RF devices. Gate density of 2100 kGate/mm2 is realized by breaking down conventional trade-off of leakage power and performance with three key approaches. 0.195 mum2 SRAM with excellent static noise margin...
An H.264/AVC encoder LSI (named SARA/E) that supports High422 profile, as well as 422 profile of MPEG-2, has been developed for HDTV broadcasting infrastructures. It contains 257GOPS motion estimation and compensation (ME/MC) engines with search ranges of -271.75 to +199.75 (H) /-109.75 to +145.75 (V), which can utilize almost all H.264/AVC ME/MC tools, multiple reference frame, variable block size,...
Increasing level of process variation in the sub-100 nm silicon technology is becoming an important issue. In this paper we describe an approach to estimate the impact of process variations on the static CMOS and the dual-rail PLA down to 32 nm process. This approach is built on accurate variation modeling, published data including the ITRS, Predictive Technology Models, and Monte-Carlo analysis....
We present the state-of-the-art 45nm high performance bulk logic platform technology which utilizes, for the first time in the industry, ultra high NA (1.07) immersion lithography to realize highly down-scaled chip size. Fully renovated MOSFET integration scheme which features reversed extension and SD diffusion formation is established to meet Vt roll-off requirement with excellent transistor performance...
This paper presents a new functional memory with a high-speed flexible data search capability. In addition to the conventional function of the exact-match data search, the proposed memory is capable of retrieving the address of stored data within a given Hamming-distance from an input data. By using the proposed dynamic threshold logic circuit, a single cycle search operation is achieved. The proposed...
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