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The threshold voltage (Vt) in scaled poly-Si channel FinFETs and tri-gate flash memories with poly-Si floating gate (FG) was systematically compared with crystal channel ones, for the first time. It was found that some superior Id-Vg characteristics are observed in the scaled poly-Si channel FinFETs with gate length (Lg) down to 54 nm or less. The standard deviation of Vt (σVt) of poly-Si channel...
The Vt variability in scaled FinFETs with gate length (Lg) down to 25 nm was systematically investigated, for the first time. By investigating the gate oxide thickness (Tox) dependence of Vt variation (VTV), the gate-stack origin, i.e., work-function variation (WFV) and gate oxide charge (Qox) variation (OCV) origin VTV were successfully separated. It was found that the atomically flat Si-fin sidewall...
In this paper, we successfully demonstrate a recessed gate normally-off GaN FET on a silicon substrate with high threshold voltage (Vth) uniformity and low on-resistance. In order to realize high Vth uniformity, a novel Vth control technique is proposed, which we call ??piezo neutralization technique??. This technique includes a piezo neutralization (PNT) layer formed at the bottom of the gate recess...
The parasitic resistance of the FinFET is investigated by the measurement based analysis. The RS/D model suggests that careful optimization as to the NiSi incorporation is necessary for the effective Rp reduction. The Rext seriously increases the Rp for TfinLt25 nm and also causes the Rp variability due to the Tfin variation.
An independent-gate four-terminal FinFET SRAM have been successfully fabricated for drastic leakage current reduction. The new SRAM is consisted of a four-terminal (4T-) FinFET which has a flexible Vth controllability. The 4T-FinFET with a TiN metal gate is fabricated by a newly developed gate separation etching process. By appropriately controlling the Vth of the 4T-FinFET, we have successfully demonstrated...
In this paper, we demonstrate CMOS characteristics on a Si(110) surface using surface flattening processes and radical oxidation. A Si(110) surface is easily roughened by OH- ions in the cleaning solution compared with a Si(100) surface. A flat Si(110) surface is realized by the combination of flattening processes, which include a high-temperature wet oxidation, a radical oxidation, and a five-step...
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