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This paper describes TSNWFET devices with embedded Si1-xGex source/drain regions and different nanowire orientations. Thick Si1-xGex embedded source/drain and lang110rang channel orientation is found effective to enhance p-channel TSNWFET performance, while cause degradation for n-channel one. Thin Si1-xGex and lang100rang channel orientation is the preferred combination for keeping n-TSNWFET performance...
For the first time, we have successfully fabricated gate-all-around twin silicon nanowire transistor (TSNWFET) on bulk Si wafer using self-aligned damascene-gate process. With 10nm diameter nanowire, saturation currents through twin nanowires of 2.64 mA/mum, 1.11 mA/mum for n-channel TSNWFET and p-channel TSNWFET are obtained, respectively. No roll-off of threshold voltages, ~70 mV/dec. of substhreshold...
This work performs a cross-sectional TEM study of holes in Si using a femtosecond laser, and observes the structure directly. Under bright-field TEM mode, a 20 to 30 nm thick amorphous layer on the silicon surface inside the hole is observed. Furthermore, an electron dispersive X-ray study proves that this layer does not contain oxygen.
Alp-buried GaAs MESFET (PB-GaAsMESFET) has been fabricated by means of implanting Be into semi-insultaing GaAs substrates to form a p-type buried layer under the channel-active layer. The experimental results show that PB-GaAs MESFET not only improve the uniformity of the pinch-off voltage but increase the transconductances and reduce the effects of back gate as well. The theoretical analysis and...
Based on two graph separator theorems, we present two unexpected upper bounds and resolve several open problems for on-line computations. (1) 1 tape nondeterministic machines can simulate 2 pushdown stores in time O(n1.5√logn) (true for both on-line and off-line machines). Together with the Ω(n1.5/√logn) lower bound, this solves the open problem 1 in [DGPR] for the 1 tape vs. 2 pushdown case. It also...
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