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In this paper we present a new approach of analyzing 3D structure for Triple-Gate MOSFETs with three different mesh regions, one at the top and two in the sidewalls of the fin, which allows the consideration of different carrier mobility at each region due to the crystalline orientation and technological processing. A procedure for the extraction of the mobility parameters in each region is developed...
The gate current present in double-gate fully depleted MOSFETs can significantly contribute to the channel current measured in these devices. For this reason, models must take account of this effect in order to represent correctly the behavior of the devices. In this paper, we report a complementation to the symmetric doped double gate model for MOSFETs, by including the presence of gate tunneling...
In this work we present: 1) Compact models for the total charges at the gate, source and drain electrodes, based on the integration of the charge densities expressions derived from the solution of the Poisson's equation in organic thin film transistors. 2) Compact models of the OTFT transcapacitances, obtained by differentiation of the charge expressions with respect to the applied voltages, and assuming...
A compact explicit model for undoped Double-Gate (DG) SOI MOSFET including velocity saturation is presented. Using this model, intermodulation linearity obtained from device level Harmonic Balance (HB) simulation and Integral Function Method (IFM) are compared.
We present a Verilog-A implementation of an Improved Charge Sheet Model (ICSM) for PD SOI MOSFETs. This model is a physical and continuous compact model for deep-submicron transistors focused in an accurate description of high order derivatives, in order to obtain good approximation of the harmonic distortion behavior. The implementation of the model, using Verilog-A language, allows analog circuit...
We review recent physics-based, compact models for thin film transistors (TFTs), including amorphous (a-Si), polysilicon (poly-Si), nanocrystalline silicon (nc-Si), and organic TFTs. The models accurately reproduce the DC characteristics for different geometries. We also present a universal TFT model paradigm, which allows to obtain a suitable estimation of TFT characteristics using only eight parameters,...
In this work we examine the electrical behavior of thin (~10 nm) SiO2/TiO2 gate insulator stacks in MOS capacitors that have undergone multiple hard breakdown events. The post-breakdown current is modeled using a simple equivalent electrical circuit consisting of a diode with series and parallel resistances. We show that the current flowing through the non-damaged oxide area still plays a significant...
In this paper an evaluation of the harmonic distortion of graded-channel SOI nMOSFETs is performed. The analysis is carried out by comparing an analytical continuous model and experimental results. The total harmonic distortion, as well as the third and second order terms are used as figures of merit in this comparison. It is shown that GC SOI devices present better gain and linearity behavior than...
In this paper we resume results obtained in the fabrication and characterization of first a-Si1-xCx:H TFTs. The behavior with temperature of these devices was studied using a unified model and extraction parameter method, UMEM, previously developed by us and applied to amorphous, polycrystalline and nanocrystalline Si TFTs as well as to organic TFTs. The behavior and variation with temperature of...
The modeling of MOSFET I-V curves for distortion analysis in analog circuit design requires compact models for both long and short channel devices, which describe the transistor behavior with high precision based on the physics of the device. In the present paper, to achieve such precision, modifications of the EKV model equations are presented, while using the same parameters. A comparison for PD...
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