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The method of substrate isolation in a typical CMOS HV technology with the addition of a deep nwell (DNW) is commonly applied in order to minimize the effect of disturbance in the substrate potential. The difficulties in identifying the true leakage path are, however, increasing as the noise current flows from this complex well structure with DNW employed in CMOS HV technology. This paper describes...
A 1V WLAN IEEE 802.11a CMOS transceiver integrates all building blocks on a single chip including a transformer-feedback VCO and a stacked divider for the synthesizer and 8-bit IQ ADCs and 8-bit IQ DACs. Fabricated in a 0.18-mum CMOS process and operated at a single 1-V supply, the receiver and the transmitter consume 85.7mW and 53.2mW, including the frequency synthesizer, respectively. The total...
An integrated analog tuner for open-cable applications is designed in a standard 0.18-mum CMOS process using single-conversion architecture. The tuner integrates a whole signal path including a wide-band low-noise amplifier, a novel image-rejection mixer, and a fully-integrated integer-N frequency synthesizer with a wide-band ring VCO. At 1.8-V supply and over the whole input frequency range from...
A high performance dielectric based antifuse field programmable gate array (FPGA) process has been developed using a standard 0.8 mu m double layer metal CMOS process. The process requires two additional self-contained modules to implement both the programmable interconnect element and the high voltage transistors required to program the antifuses. The antifuse is 8.4 nm ONO dielectrics. The high...
Compact, low-resistance oxide-nitride-oxide (ONO) antifuses are studied for time-dependent dielectric breakdown (TDDB), program disturb, programmed antifuse resistance stability, and effective screen. ONO antifuses are superior to oxide antifuses. No ONO antifuse failures were observed in 1.8 million accelerated burn-in device-hours accumulated on 1108 product units. This is in agreement with the...
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