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This paper presents a power-efficient single-loop continuous-time (CT) third-order sigma delta (ΔΣ) modulator that achieves a SNDR of 79.6 dB over a 10 MHz signal bandwidth. The modulator uses a feedforward-feedback (CIFF-FB) architecture which incorporates a single amplifier biquad (SAB) and a passive integrator to realize a third-order noise shaping. We also propose a continuous-time complementary...
Wireless communication systems and Ethernet networks call for moderate-resolution GS/s energy-efficient ADCs. While previous work [1] shows that the multi-bit per cycle SAR ADC can achieve low power due to various hardware reduction techniques, there are still a few limitations that restrain this architecture. First, the pre-charge slows down the logic and the DAC settling, especially during the MSB...
This paper presents a calibration scheme for reference error caused by signal dependent switching transient in a high speed SAR ADC. The scheme has a little hardware overhead, which is not dependent on the type of the input signal and is able to run in the background without interrupting the ADC's normal operation. The calibration along with the SAR ADC are implemented in a 65 nm CMOS and the measurement...
This paper presents a 12b 180 MS/s partial-interleaving Pipelined-SAR analog-to-digital converter (ADC). The 1st-stage is implemented with a 2b/cycle SAR ADC for high speed, where we propose a merged-residue-DAC technique to improve the noise performance. The capacitor pre-charging in conventional 2b/cycle operation wastes settling time and switching energy, while with this design approach the switching...
Taking the factor of customer switching into count, we analyze duopoly models in which both start-ups and established firms consider the competitive investment in R&D when they enter the new market. Firms make a decision on investment will influence the customer switching. The firms with investment may attract new customers from other firms which does not invest and then maintain more market share...
This paper presents a monotonic multi-switching technique that is implemented in a 8b SAR ADC. The proposed switching reduces 1/2 total DAC capacitance and achieves more than 80% switching energy saving when compared to the most advanced VCM-based or merged capacitor switching methods. Besides, conversion redundancies are added to compensate the errors resulting from insufficient DAC settling and...
Novel self-timing switch-driving registers for high-speed successive approximation register (SAR) ADC is proposed. This circuit can provide fast charging path from comparator output to DAC array of SAR ADC and store the comparison results simultaneously at each approximation bit-cycle. The propagation delay from input to output of the register is about 60 ps only in a 90 nm CMOS process. By using...
Regression is an important prediction method to establish models between variables. The primitive regression algorithms ignore the sample weights, and consider all samples play an equal role in regression. But this kind of algorithms often loses efficacy when dealing with outliers, since outliers disturb the regression models greatly. For traditional switching regression, sample membership varies...
A novel capacitor array structure for successive approximation register (SAR) ADC is proposed. This circuit efficiently utilizes charge recycling to achieve high-speed of operation and it can be applied to low-to-medium-resolution, high-speed SAR ADC's. The parasitic effects of the proposed structure are analyzed theoretically and behavioral simulations are presented to verify the circuit's performance...
A novel capacitor array structure for successive approximation register (SAR) ADC is proposed. This circuit efficiently utilizes charge recycling to achieve high-speed of operation and it can be applied to high-speed and low-to-medium-resolution SAR ADC. The static linearity performance, namely the INL and DNL, of the proposed structure is theoretically analyzed and behavioral simulations are performed...
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