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A comprehensive study implementing a high-k/metal gate stack on Si(110) substrates has been performed, including a comparison of HfO2 and HfSiON, and compatibility with strain engineering. We demonstrate p-channel MOSFETs (pFETs) with optimized atomic layer deposited (ALD) HfO2 on Si(110) substrates with a ~ 3.3times high field hole mobility (μh) enhancement vs. a Si(100) substrate. On-state drain...
We demonstrate, for the first time, a HfLaSiON/metal gate stack that concurrently achieves the following: low threshold voltage (VT =0.33V), low equivalent oxide thickness (EOT=0.91nm) (Tinv =1.3nm) and 83% SiO2 mobility. Key enablers of this result are 1) La doped HfSiON for n-FET VT tuning 2) HfO2:SiO2 alloy ratio with 10% SiO2 suppressing crystallization up to 1070degC, 3) interlayer SiO2 (IL)...
Positive constant voltage stress combined with charge pumping (CP) measurements was applied to study trap generation phenomena in SiO2 /HfO2/TiN stacks. Using the analysis for frequency-dependent CP data developed to address depth profiling of the electron traps, we have determined that the voltage stress-induced generation of the defects contributing to threshold voltage instability in high-k gate...
Constant voltage stress (CVS) combined with charge pumping (CP) measurements was applied to study trap generation phenomena in SiO2 /HfO2/TiN stacks. Using the analysis for frequency-dependent CP data developed to address depth profiling of the electron traps, we have determined that the voltage stress-induced generation of the defects contributing to threshold voltage instability in high-k gate stacks...
We show an ALD based HfSiON gate dielectric scaled to 1 nm EOT with excellent performance and reliability. Furthermore, the HfSiON dielectric films are integrated in a gate first approach that includes a 1000degC-5s anneal. It is also demonstrated that this 1 nm EOT HfSiON can achieve electron and hole mobilities comparable to that of SiON. This progress is enabled due to better understanding of the...
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