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A leading edge 32 nm high-k/metal gate transistor technology has been optimized for SoC platform applications that span a wide range of power, performance, and feature space. This technology has been developed to be modular, offering mix-and-match transistors, interconnects, RF/analog passive elements, embedded memory, and noise mitigation options. The low gate leakage of the high-k gate dielectric...
It is desirable for many power applications to integrate a power switch and its reverse-parallel diode onto the same chip/package to reduce component count and improve circuit reliability and integrity. In this paper, a SiC vertical JFET with a monolithically integrated JBS diode is proposed, fabricated and characterized. The integrated switch uses a process similar to that of a traditional SiC vertical...
I Power integrated circuit based on SiC lateral JFET promises to operate at temperatures beyond 300degC. In this paper, design constraints in selecting the LJFET threshold voltage, the load resistance and the DC power supply voltage to obtain proper gate driver circuit functionality in the temperature range of 25degC~300degC are investigated through extensive experimentation. The study shows that...
Highly scaled FinFET SRAM cells, of area down to 0.128 m2, were fabricated using high-kappa dielectric and a single metal gate to demonstrate cell size scalability and to investigate Vt variability for the 32 nm node and beyond. A single-sided ion implantation (I/I) scheme was proposed to reduce Vt variation of Fin-FETs in a SRAM cell, where resist shadowing is a great issue. In the 0.187 m2 cell,...
At the 22 nm node, we estimate that superior electrostatics and reduced junction capacitance in FinFETs may provide a 13~23% reduction in delay relative to planar FETs. However, this benefit is offset by enhanced gate-to-source/drain capacitance (Cgs) in FinFETs. Here, we measure FinFET Cgs capacitance at 22 nm-like dimensions and determine that, with optimization, the FinFET capacitance penalty can...
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