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Pentacene organic thin-film transistors (OTFTs) with HfLaO high-κ gate dielectric were fabricated. The dielectric was prepared by a sputtering method and then annealed in N2, NH3, O2, or NO at 400 °C. The carrier mobility of the NH3-annealed OTFT could reach 0.59 cm2/V · s, which is higher than those of the other three devices. Moreover, the NH3-annealed OTFT obtained the smallest subthreshold swing...
Pentacene OTFTs with HfLaO or HfO2 as gate dielectric were fabricated. The dielectrics were prepared by sputtering method and then annealed in NH3 at 400 oC. The k value for the HfLaO and HfO2 films amounted to 12.3 and 11.8 respectively. Both of the OTFTs could operate with a supply voltage of -5 V. The mobility of the OTFT with HfLaO gate dielectric was 0.688 cm2/Vs, which was much higher than that...
Reliability of charge trapping (CT) devices has been examined in detail, and the path to sub-30nm NAND flash is investigated. All CT devices are vulnerable to edge effects (non-uniform injection and non-uniform Vt along the device width). This degrades both the endurance and the ISPP programming efficiency, but the effect can be minimized by careful engineering. Metal gate and high-K dielectric can...
Barrier engineered charge-trapping NAND flash (BE-CTNF) devices are extensively examined by theoretical modeling and experimental validation. A general analytical tunneling current equation for multi-layer barrier is derived using WKB approximation. The rigorously derived analytical form is valid for both electron and hole tunneling, as well as for any barrier composition. With this, the time evolution...
This paper carefully analyzes various charge-trapping NAND Flash devices including SONOS, MANOS, BE-SONOS, BE-MANOS, and BE-MAONOS. The erase mechanisms using electron de-trapping or hole injection, and the role of the high-k top dielectric (Al2O3) are critically examined. In addition to the intrinsic charge-trapping properties, the STI edge geometry in the NAND array also plays a crucial role in...
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