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Several approaches of solid phase epitaxy (SPE) formed embedded SiC (eSiC) scheme have been investigated on 28 nm node technology. The single SPE thermal process by LSA only with post S/D scheme is reported to accommodate high carbon concentration as well as low sheet resistance in this work. Cluster carbon with tilted angle implantation is designed to further simplify process and increase channel...
SONOS devices using gate injection programming and erasing have better cycling endurance because the gate oxide is not stressed by P/E operations. This work studies the gate injection behavior in detail using the recently developed gate-sensing and channel-sensing (GSCS) technique. GSCS accurately locates the charge centroid during programming/erasing and reliability tests. For the first time, we...
The role of AI2O3 in MANOS device is critically examined, and we conclude that its primary function is to reduce gate injection during erase operation. By itself, AI2O3 cannot stop charge leakage from the charge-trapping nitride layer. Furthermore, AI2O3 provides no magic during the erase operation, and MANOS erases very slowly through charge de-trapping. BE-SONOS [1], with the band engineered ONO...
In this paper, dopant segregation (DS) method is adopted to enhance device performance of PtSi-based Schottky-barrier source/drain MOSFETs (SB-MOSFETs) fabricated on ultrathin silicon-on-insulator. The DS formation is realized by means of Silicide As Diffusion Source. Without DS treatment, the devices are typically p-type, but with a rather large electron branch at positive gate bias. Dopant segregation...
Multi-bit/cell nitride trapping NVM (Eitan et al., 2000 and 2005) using BTBT-HH erase suffers an "apparent" VT loss due to interface trap (NIT) generation. The array-nitride-sealing (ANS) ONO process (Shih et al., 2005) eliminates this VT loss by blocking hydrogen from the interface. In this work we further outfit the ANS-ONO process with a nitridized Si/SiO2 interface. By introducing a...
For the first time, a successful TFT NAND-type flash memory is demonstrated using a low thermal budget process suitable for stacking the memories. A TFT-SONOS device using bandgap engineered SONOS (BE-SONOS) (Lue, et al. 2005) with fully-depleted (FD) poly silicon (50 nm) channel and tri-gate P+-poly gate is integrated into a NAND array. Small devices (L/W=0.18/0.09 mum) with good DC performance are...
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