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We propose a new scheme of dynamic nets-to-TSVs assignment during floorplanning for 3D-ICs. A nontrivial area occupied by TSVs, their physical dimensions, location on the layout and the nets-to-TSVs assignment, are some of the key factors influencing the wirelength, TSV count and chip area, and consequently, impact the total delay. We address the above issues by simultaneous placement of TSV islands...
We propose a new floorplanning approach for TSV-based 3D ICs. A non-negligible area occupied by TSVs, TSVs physical locations and nets-to-TSVs assignment considerably influence chip area, wirelength and delay. TSVs also induce significant thermo-mechanical stress in nearby silicon. The proposed approach addresses the above issues by co-placement of TSVs with circuit blocks, and concurrent nets-to-TSVs...
3D-IC technology discussed in this paper is based on vertical stacking of dies connected by through-silicon-vias (TSV). Vertical stacking helps reducing the wirelength but TSVs occupy space on device layers and their actual positions, arrangement, and physical properties determine the total wirelength. They also introduce thermo-mechanical stress that alters properties of devices that are close to...
3D-IC design facilitates reduction in wirelength by vertically stacking dies. Through-silicon-vias (TSVs) are used to connect inter-die signals. The dynamic power consumption of interconnects in 3D-IC is contributed by wires, buffers and TSVs. The delay in interconnects for 3D-IC is greatly influence by TSV capacitance. In this paper we propose TSV capacitance-aware 3D floorplanning to reduce the...
3D integration is considered as one of the most promising solutions to improve energy efficiency of heterogeneous ICs. We use floorplannning tools to evaluate power consumption related to inter-block connections for digital ICs implemented as 2D and 3D systems. We focus on 3D stacking using through-silicon-vias (TSVs). We evaluate contributions of wires, buffers and TSVs based on information available...
We present a novel 3D floorplanning algorithm with module splitting (3D-FMS). The proposed methodology allows designers to introduce and evaluate an assignment of vertically-aligned parts of the same module to different device layers. Our experimental results on MCNC and GSRC benchmarks show that 3D-FMS can generate a good floorplanning solution with reduced wirelength inside modules and optimized...
We have extended three existing 3D wirelength distribution models, initially developed for square modules, to handle rectangular 3D blocks. Our extended models enable the stochastic wirelength prediction from 3D chip level to 3D block level. We have performed comparative and qualitative studies of these newly developed rectangular models. Experimental results provide a comparative picture in terms...
Noise generated by digital sub-circuits becomes a serious problem in fast mixed signal system on chips (SoCs). Digitally generated noise corrupts supply voltages and is propagated inside a silicon substrate as so called substrate noise. The circuits for substrate noise suppression proposed so far have serious weaknesses due to their frequency limitations. We present a method for optimization of noise-suppressive...
Carbon Nanotube FET (CNT-FET) is a promising candidate for the construction of future integrated circuits. However the presence of metallic tubes negatively affects delay, leakage power, and yield of such circuits. In this paper we compare four different CNT-FET configurations - shared tube, parallel tubes, transistor stacking, and tube stacking. In the presence of 10% metallic tubes, stacking configurations...
An analytical method for power supply spectrum estimation to be used in early system planning is proposed. The method is based on a careful evaluation of a number of parameters of an equivalent inverter; rise time, fall time and widths of current impulses. We assume an inverter to be a basic building component of digital blocks. Using the proposed method one can determine estimates of power supply...
Classical two-variable symmetries play an important role in many EDA applications, ranging from logic synthesis to formal verification. This paper proposes a complete circuit-based method that makes uses of structural analysis, integrated simulation and Boolean satisfiability for fast and scalable detection of classical symmetries of completely-specified Boolean functions. This is in contrast to previous...
This paper presents an efficient method for supply-current spectrum estimation for the static CMOS family of digital gates. It extends the previous approach (Blackiewicz, 2006), that considered only the noise due to a gate output switching, by including the noise generated by glitching, and short impulses. Estimation of digital circuit noise is used in early design planning of modern mixed-signal...
We consider a test-scheduling problem, with layout constraints, for core-based SOCs. Individual cores have to be tested on a system level after manufacturing and therefore special test access mechanisms (TAMs) are required. The amount of additional wires needed to route TAMs depends strongly on a SOC layout. In this research, we investigate the SOC test-scheduling problem formulated as the bin-packing...
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