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Gate-first integration of tunable work function metal gates of different thicknesses (3-20 nm) into high-k/metal gates CMOS FinFETs was demonstrated to achieve multiple threshold voltages (VTh) for 32-nm technology and beyond logic, memory, input/output, and system-on-a-chip applications. The fabricated devices showed excellent short-channel effect immunity (drain-induced barrier lowering ~40 mV/V),...
For the first time, a novel damage-free neutral beam-assisted atomic etching process has successfully demonstrated the removal of the residual high-k dielectric layer after gate patterning. Due to its neutralized atomic flux and chemical reaction, high etch selectivity is observed to improve device performance and reliability. This process should significantly enhance high-k/metal gate manufacturability.
This paper reports on a scalable and simple gate-first integration option for manufacturing the high-k/metal gate CMOS transistors targeting sub-32 nm LSTP applications: Vt < plusmn 0.45 V (at Lg = 60 nm) at EOT les 1.4 nm, with 105 times Jg reduction compared to SiO2. This scheme integrates several simplifications and improvements for the first time: single metal gate material, single channel...
In this paper we investigate state-of-the-art undoped channel FinFETs and FinDiodes with an emphasis on I/O and ESD applicability. Utilizing electrical characterization data, 3D TCAD, and a compact model, we demonstrate that FinFETs and FinDiodes exhibit a very appealing combination of high breakdown voltage and low Ioff for I/O and ESD protection circuit applications.
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