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With the rapid increase in the number of processor cores on a chip, packet-switching networks on chip (NoCs) have emerged as a promising paradigm for designing scalable communication infrastructures for future multi-core processors. The quest for high-performance networks, however, has led to very area-consuming and complex routers with marginal return in performance. On the other hand, studies show...
Aimed at the parasitic oscillation phenomenon existing in rectifier output of DC-DC converter, a new symmetrical RCD clamp circuit is designed to suppress the voltage spike and reduce the energy loss, while achieving switching inverted in zero-voltage. The main circuit topology is given, in the same time, a detailed analysis of the clamp circuit working principles, characteristics and parameters of...
Prior studies on packet-switching on-chip networks have primarily focused on the micro architecture of the router to reduce the communication latency. In this paper, we propose a novel interconnection topology for mesh-connected processor arrays. By sharing routers among PEs and PEs among routers, our network significantly reduces the average hop count for a packet, thereby reducing the network latency...
With the rapid increase of processing elements (PEs) on a single chip, the communication network poses a major limiting factor for both performance and power consumption in future SoCs. This paper presents a low-area and low-latency wormhole-switching network on chip (NoC). By introducing a new PE-router organization, our design not only reduces the total number of routers for a given number of PEs,...
Recent significant advancements in FPGAs have made it viable to explore multiprocessor solutions on a single FPGA chip. An efficient communication architecture that matches the needs of the target application is always critical to the overall performance of multiprocessors. Packet-switching network-on-chip (NoC) approaches are being offered to deal with scalability and complexity challenges coming...
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