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This presentation will highlight some of the challenges and opportunities that test developers and test operations managers face in a changing data climate. Measured data will drive decisions not only about the product under test, but potentially on the entire design and manufacturing ecosystem. I will also explore some of the value tradeoffs of increased data harvesting vs. reduced test cost requirements...
Presents the introductory welcome message from the conference proceedings. May include the conference officers' congratulations to all involved with the conference event and publication of the proceedings record.
After many years of relying on established processes technology geometries, advanced automotive semiconductors, driven by assisted and autonomous driving systems, have recently joined the race to ever smaller semiconductor process technologies. If the massive functionality enabled by 16-nm and below FinFET semiconductor processes, combined with the new fault mechanisms they bring along, weren't enough...
Low-area energy-efficient security primitives are key building blocks for enabling end-to-end content protection, user authentication and data security in IoT platforms. This talk describes the design of security circuit primitives that employ energy-efficient circuit techniques with optimal hardware-friendly arithmetic for seamless integration into area/battery-constrained IoT systems: 1) A 2040-gate...
Manual wafer-level die inking is a common procedure for excluding die locations that are likely to be defective. Although this is a more cost-effective process, as compared to the expensive burn-in tests, it remains a labor-intensive step during IC testing. For each manufactured wafer, test engineers have to visually inspect every failure map in order to identify any regions where additional die need...
Due to technology scaling, which means smaller transistor, lower voltage and more aggressive clock frequency, VLSI devices are becoming more susceptible against soft errors. Especially for those devices deployed in safety- and mission-critical applications, dependability and reliability are becoming increasingly important constraints during the development of system on/around them. Other phenomena...
Given the fast growing complexity and miniaturization of automotive SoCs, this paper presents functional safety challenges and related solutions for such SoCs. The paper is based on ISO 26262 standard and shows experimental results on a SoC example to demonstrate the advantages of the proposed solutions.
The quality level of mixed-signal ICs lags behind the below-part-per-million defect test escape rates of digital ICs, as a result of the traditional testing based on performance specifications. Methods increasing the controllability to solve the problem of the low fault coverage of analog and mixed-signal circuits are in practice limited due to the excessive area overhead they require and their impact...
Diagnosing chain failures is extremely important to ramp up production yield. Use of modern day low pin compressors limit the observability making chain diagnosis a difficult problem. When multiple chains fail during initial ramp up of yield, the high-resolution patterns are generally used for diagnosis. These patterns are generated using special ATPG settings and are very high in numbers. These high-resolution...
The prevalence of bridging defects makes bridging fault models important to consider during fault simulation and test generation. The large number of bridging faults that can be defined for a circuit led to the development of procedures for selecting subsets of bridging faults that are likely to occur based on the circuit layout, and hard-to-detect bridging faults whose coverage provides a more effective...
This paper shows new insights on the stochastic nature of aging-related timing impact in digital circuits. Varying critical paths through aging trigger the need for aging compensation control loop based on an unsupervised machine learning algorithm. Adaptive Resonance Theory (ART) algorithm is favored for its ability to handle the stability-plasticity dilemma.
The ITC'97 analog and mixed-signal (A/MS) benchmark circuits have been available for two decades. This paper discusses why they were useful but not for comparing A/MS design-for-test (DFT) techniques, tests, or fault coverage. First, this paper discusses these and other benchmark circuits, and proposes objectives for better benchmark circuits. The paper then describes the first, publicly-available...
Advances in semiconductor device manufacturing technology, which have enabled reduced feature size and higher integration, have resulted in a gap between the defect level estimated at the design stage and that reported for fabricated devices. As one possible strategy to control test quality and cost, the authors have proposed weighted fault coverage estimation. In this study, we propose layout-aware,...
Static test compaction procedures that modify tests perform the modification so as to increase the number of faults that some of the tests detect, thus making other tests unnecessary. Tests that become unnecessary are removed from the test set without reducing the fault coverage. This paper describes a static test compaction procedure of this type for transition faults that has the following additional...
Excessive IR-drop during scan shift can cause localized IR-drop around clock buffers and introduce dynamic clock skew. Excessive clock skew at neighboring scan flip-flops results in hold or setup timing violations corrupting test stimuli or test responses during shifting. We introduce a new method to assess the risk of such test data corruption at each scan cycle and flip-flop. The most likely cases...
In order to reduce the power consumption and improve the circuit performance, the dual-edge triggered flip-flop (DETFF) has been using as sequential element in the designs. Comparing with conventional single-edge triggered flip-flop (SETFF), applying the scan based structural test for the designs using DETFFs faces additional challenges. In this paper, we address some of the challenges, including...
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