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A novel run-pause-resume (RPR) debug methodology that can achieve complete cycle-level granularity of debug resolution for multiple clock domain systems is proposed. With this methodology one can pause the normal operation of a system at any cycle of any clock domain and resume the system without causing any data invalidation problem. Bidirectional transactions among different clock domains are analyzed...
Static test compaction procedures that modify tests perform the modification so as to increase the number of faults that some of the tests detect, thus making other tests unnecessary. Tests that become unnecessary are removed from the test set without reducing the fault coverage. This paper describes a static test compaction procedure of this type for transition faults that has the following additional...
Excessive IR-drop during scan shift can cause localized IR-drop around clock buffers and introduce dynamic clock skew. Excessive clock skew at neighboring scan flip-flops results in hold or setup timing violations corrupting test stimuli or test responses during shifting. We introduce a new method to assess the risk of such test data corruption at each scan cycle and flip-flop. The most likely cases...
This work studies a data-driven methodology for detecting systematic defects using layout-aware scan diagnosis data. As part of volume diagnosis, this methodology focuses on ranking the most systematic defective signatures, while possible random defects are also present in the wafer. The main analysis components utilize χ2 Independence Tests to establish systematic relationships between reported defective...
Semiconductor design houses are increasingly becoming dependent on third party vendors to procure intellectual property (IP) and meet time-to-market constraints. However, these third party IPs cannot be trusted as hardware Trojans can be maliciously inserted into them by untrusted vendors. While different approaches have been proposed to detect Trojans in third party IPs, their limitations have not...
Yield improvement, yield ramp, and defect screening have been major areas of concern for the semiconductor industry as technology nodes have advanced. Much effort has been focused on capturing the defects missed by traditional stuck-at and transition delay fault model based testing. A majority of these un-modeled defects stems from features inside a standard cell or between two adjacent standard cells...
With a relatively small number of components, analog ICs are much more vulnerable to piracy, and especially reverse engineering, than many digital ICs. However, analog IC security has received much less research attention than digital ICs. We introduce a combinational locking technique using configurable current mirror for analog IC protection. The locking circuit is designed by applying Satisfiability...
A test reordering algorithm is presented to improve the results of scan chain diagnosis when a limited amount of fail data is collected by the tester. Tests are reordered based on information derived by applying an enhanced defect diagnosis procedure to the faulty units with scan defects. Tests that are found important for diagnosis of more faulty units are placed earlier in the test set based on...
Scan shift power consumption is one of the major concerns in low power circuits. While there are multiple design for testability (DFT) techniques proposed in the literature for addressing both peak and average shift power optimization, most of the solutions impose additional design overhead which may impact functional performance of the device. In this paper, we propose a novel frequency scaled segmented...
Spectral testing and linearity testing are two important categories in ADC testing. The sampling clock quality is a crucial factor in ADC spectral testing. The cumulative clock jitter of the sampling clock generates power leakage in the fundamental component of the ADC output spectrum, and the random clock jitter increases the noise floor of the ADC output spectrum, which corrupts the spectrum result...
In order to reduce the power consumption and improve the circuit performance, the dual-edge triggered flip-flop (DETFF) has been using as sequential element in the designs. Comparing with conventional single-edge triggered flip-flop (SETFF), applying the scan based structural test for the designs using DETFFs faces additional challenges. In this paper, we address some of the challenges, including...
Volume Diagnosis is a proven methodology to significantly improve the yield enhancement rates. One of the key factors of success to this methodology is being able to perform diagnosis on hundreds to thousands of failing dies using a limited amount of computational resource in a tractable time. This paper presents a new Multiple Device Diagnosis (MDD) system to significantly improve the throughput...
Presents the introductory welcome message from the conference proceedings. May include the conference officers' congratulations to all involved with the conference event and publication of the proceedings record.
Three dimensional (3D) integration based on through-Silicon-Via (TSV) is currently evolving as an area of great interest in modern semiconductor industry. 3D integration provides higher performance, bandwidth and lower power consumption. But due to scaling in technology features these chips are more complex. Hence, testing of these 3D integrated circuits (ICs) is a challenging task. Effective test...
Localized small delay defects, for example due to degraded transistor drive strength caused by a broken fin, are a growing concern in current FinFET and emerging gate all around (GAA) technologies. Such defects are currently targeted by timing-aware Transition Delay Fault (TDF) tests that aim to test the target nodes along the longest path. The resulting tests often require considerable test generation...
Through four use cases with examples, we describe how IEEE 1687 can be extended to include analog and mixed-signal chips, including linkage to circuit simulators on one end of the ecosystem and ATE on the other. The role of instrumentation, whether on the tester or on the device itself, is central to analog testing, and conveniently also the focal point of IEEE 1687. We identify enhancements to the...
This paper proposes a fast-Fourier-transform-based jitter separation and model-based bit-error-rate (BER) curve estimation technique for analyzing asymmetric total jitter distributions. The proposed method assumes asymmetric deterministic jitter models which have distributions denoted by even and odd functions. It separates deterministic jitter and random jitter by identifying the model parameters...
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