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An effective method is proposed to reduce dynamic power for synchronous 2-read/write (2RW) 8T dual-port (DP) SRAM. Adjusting the wordline (WL) pulse timing control circuit is newly introduced for both reading and writing operations. Row addresses of port-A and port-B are compared. The same row access is detected or not in each cycle, which is an inherent access mode of 2RW 8T DP SRAM. In different...
This work presents an ultra-low phase noise and all-digital frequency generator, providing multiple output-frequencies. In a time-interleaved fashion, the proposed calibrator can continue to correct the multiple output-frequencies of injection-locked DCOs, which can change independently between 0.9 and 1.2GHz. Due to the time-interleaved calibrator, operating continuously in the background, each injection-locked...
A power-efficient analog beamforming embedded SAR ADC for ultrasound imaging systems is presented. It is constructed from multiple sub-beamforming SAR ADCs, which sequentially perform analog beamforming and analog-to-digital conversion for an assigned focal point on a scan-line. Power is saved because these operations are carried out in the charge domain without a summing op-amp. This is realized...
This paper presents a fractional-N sub-sampling phase-locked loop (SSPLL) for spread-spectrum clock generator. A digital-to-time converter (DTC) is adopted to facilitate a fractional-N SSPLL. A digital calibration scheme is employed to eliminate DTC gain error. With the calibration method enabled, the PLL is successfully locked and achieves 18.98-dB EMI reduction. This PLL was fabricated in a TSMC...
A dual strong-arm (DSA) comparator is designed targeting at low-voltage operation in deeply-scaled technologies. The addition of a second regenerative latch helps reduce both offset sensitivity and offset while maintaining comparable or better performance as a conventional double-tail latch across a wide range of voltages. A large comparator offset measurement array is fabricated in a 28nm FDSOI process...
A dual-mode NRZ/PAM-4 differential low-swing voltage-mode transmitter employs a quarter-rate output multiplexing architecture for low-power operation. In NRZ mode, 2-tap feedforward equalization is realized with analog replica-bias tap control that is configurable in high-performance controlled-impedance or energy-efficient impedance-modulated settings. This analog control also allows for efficient...
This paper presents a 16-channel analog front-end (AFE) for wearable dry EEG recording. A novel AFE architecture that combines time division multiplexing (TDM) and chopping stabilization (CS) to improve the system common mode rejection ratio (CMRR) and the input-referred noise is proposed. With TDM, the reference electrode is connected to single channel input during its time slot to avoid the CMRR...
This paper presents a new concept of PUF based on a chaotic behavior. Chaos is essentially not a random phenomenon but a deterministic non-periodic flow which can be utilized to extract reproducible unique ID entropy. The strong parametric sensitivity of the chaos guarantees ID variety and unclonability over unpredictable manufacturing variations. An undesirable disturbance due to dynamic parametric...
A new switched capacitor (SC) converter for powering miniature sensor systems with wide load current and output voltage ranges is proposed in this paper. By adopting a multiple-ratio SC stage and reconfigurable stage interconnect scheme, the proposed converter offers fine granularity of conversion ratios, which improves efficiency for light load operation. The multiple-leaf structure for switch size...
Word-line Batch Vth Modulation (WBVM) is proposed as a comprehensive solution for both write-hot and cold data to improve the reliability of Triple Level Cell (TLC) NAND Flash memories. For write-hot data, WBVM Vth score modulation decreases the program-disturb errors by 49% and enhances the endurance by 1.8-times of 2D-TLC NAND Flash. On the other hand, for write-cold data, WBVM BER score modulation...
A 56Gbps PAM-4 optical receiver front-end is presented. In order to reduce the input-referred current noise of the receiver front-end, the shunt feedback resistor Rf of the TIA is enlarged. And, the equalizer is inserted to boost the high-frequency gain and extend the bandwidth. The AGC amplifier using the proposed dB-linear VGAs is further to lower the noise. This PAM-4 optical receiver front-end...
This paper presents an ultra-low power 32.768-kHz fractional-N phase-locked loop (PLL). Several circuit techniques are adopted to facilitate low-power operation. A duty-cycled control scheme is proposed to turn off the charge pump intermittently for energy saving. In the VCO, a near-off switch is applied to implement a large resistor, leading to a lower power consumption and smaller chip area. Furthermore,...
Dedicated hardware accelerators enable energy-efficient implementations of radio and imaging basebands. Multistandard, multi-mode radio basebands require an on-the-fly reconfigurable fast Fourier transform (FFT) accelerator that implements many different FFT sizes. An instance of a runtime-reconfigurable 2n3m5k FFT accelerator was generated by a custom hardware generator to meet the requirements of...
A 6-bit time-based folding matrix multiplication technique for support vector machine (SVM) classification is proposed. A voltage controlled oscillator (VCO) based analog-to-digital converter (ADC) performs in-situ matrix multiplications (MM) along with analog to digital conversion. It also offers a low supply voltage of operation (down to 0.4V) and an input range of 0.8V, drawing a total of 376nA...
This paper presents a power-efficient single-loop continuous-time (CT) third-order sigma delta (ΔΣ) modulator that achieves a SNDR of 79.6 dB over a 10 MHz signal bandwidth. The modulator uses a feedforward-feedback (CIFF-FB) architecture which incorporates a single amplifier biquad (SAB) and a passive integrator to realize a third-order noise shaping. We also propose a continuous-time complementary...
This paper describes a WiFi/BT combo SoC with integrated dual-band PAs, LNAs and T/R switches, supporting concurrent receiving for improved throughput by 30% in dense networking environment of 2.4GHz ISM band and wide-range transmitting capability (>20dB) while keeping good output power accuracy and PA power efficiency. The measured 2.4GHz/5GHz WiFi 54Mbps RX sensitivity is −78.2/−78.1dBm and Pout...
We propose an on-chip bias temperature instabilities (BTI) monitor by using standard cell based unbalanced ring-oscillator (RO). The monitor consists of NAND and NOR with extremely large difference in drive strength, which enables 4.2x sensitivity to BTI compared with normal INV based RO. This originates not only from accentuation of the degraded stage with small drive strength by the dominant delay...
This paper designed a 1-Mb HfOx-based embedded Resistive Random Access Memory (RRAM) device with a one-transistor-one-resistor (1T1R) structure, and systematically investigated its working temperature range. It noted that this embedded RRAM macro has a 1.6X working temperature range than previous design for some extreme environment. Using the peripheral-assisted technique, it can enable the error...
This paper reports a 3.0 THz detector which can detect the terahertz wave radiated by a quantum cascade laser (QCL) working at pulse mode. The detector was implemented in a 65 nm silicon CMOS process. The chip size is 1.5×l.5 mm2 including bonding pads. THz detector using FET is based on plasma wave theory proposed by Dyakonov and Shur which allows detection of THz radiations far beyond the FET devices...
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