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An effective method is proposed to reduce dynamic power for synchronous 2-read/write (2RW) 8T dual-port (DP) SRAM. Adjusting the wordline (WL) pulse timing control circuit is newly introduced for both reading and writing operations. Row addresses of port-A and port-B are compared. The same row access is detected or not in each cycle, which is an inherent access mode of 2RW 8T DP SRAM. In different...
We examine appropriate bitcell layouts for two read/write (2RW) 8T dual-port (DP) SRAM in advanced planar/FinFET technologies. 256-kbit 2RW DP SRAM macros with highly symmetrical 8T DP bitcell were designed and fabricated using 16 nm FinFET technology. The read/write assist with wordline overdrive reduces Vmln by 120 mV, achieving successful operation at below 0.5 V.
An embedded single-port SRAM with cost effective test screening circuitry is demonstrated for low-power micro controller units (MCUs). The probing test step at low-temperature (LT) of −40°C is eliminated by imitating pseudo LT conditions in the final test step where a sample is measured at room temperature (RT). Monte Carlo simulation is carried out with consideration of global and local Vt variations...
A 2-read/write dual-port SRAM and 1-read/1-write two-port SRAM with stable operation at temperatures of −40 to 170°C are implemented in 40 nm embedded flash CMOS technology for automotive microcontroller applications. To reduce the leakage current and to ensure the read/write operating margin at over 125°C, a new 8T SRAM bitcell with the optimized process and sizing is proposed. A test circuit for...
A 160 kb SRAM macro with stable operation under widely various temperatures of −40 to 170°C is implemented in 40 nm embedded flash CMOS technology for automotive microcontroller applications. We finely optimized MOS sizes of the 6T SRAM bitcell with process tuning to enhance the read margin and to reduce leakage power at high temperatures over 125°C. The optimized bitcell improves the static-noise-margin...
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