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Novel 3.3-kV trench IGBT with low loss and low dvAK/dt noise was developed. The structural feature of the IGBTs is deep p-WELL layers separated from trench gates. This structure suppresses excess VGE overshoot and then reduces recovery dvAK/dt. Moreover, this effect is enhanced by reducing the resistance of the deep p-WELL layers (RFP). It was found that, for the first time, the trade-off characteristics...
In this paper, a balanced High Voltage (HV) IGBT is presented. The proposed HV IGBT is composed of three technologies: Wide Cell Pitch CSTBTTM(III) for cell structure, Partial P collector utilizing LPT(II) buffer for vertical structure, and a novel area-efficient edge termination design. We called the above edge termination design “Linearly-narrowed Field Limiting Ring (LNFLR)”. The experiment results...
Silicon on insulator (SOI) technology for power devices offers many distinct advantages compared to bulk Si technology, however in high power applications the buried oxide (BOX) layer can impede heat transport towards the backside of the silicon substrate. This paper demonstrates integration of heat sinks in SOI power devices to improve thermal performance. The heat sinks are formed by polysilicon...
Trench-filling technology realizes an outstanding productivity for fabricating the Super Junction (SJ) structure of SJ-MOSFETs. However, crystal defects that occur during epitaxial growth are causing poor electrical characteristics. Our optimized process reduced the number of crystal defects from over 2000/mm2 to under 10/mm2. As a result, we have achieved both low loss and low leakage current and...
Two low reverse recovery charge solutions for 30-V power MOSFETs are proposed. One solution is a device consisting of a MOSFET and a Schottky barrier diode (SBD) in a single chip featuring a double epi structure to enhance the breakdown voltage. The other solution is a device with an integrated SBD in every unit cell that can achieve a high threshold voltage via the P− layer with Schottky contact...
Novel Interdigitated LDMOS is experimented resulting in best in class RSP-BVDSS performance (21.8mΩ-mm2 with BVDSS of 47V) in comparison to published LDMOS. RSP improvement is made through additional current path by removing STI region in drift area. Breakdown voltage is maintained with lateral field plate effect from side of the current path. Proposed Interdigitated LDMOS satisfies reliability criteria...
The small- and large-signal output capacitances of a super junction MOSFET and a conventional power MOSFET are obtained as a function of voltage and compared. The capacitors are charged and discharged by a voltage pulse through an external resistor and the voltage and current across the capacitors are measured as a function of time. The stored charge in the nonlinear output capacitor is shown to be...
This paper reports that theoretical limits for the superjunction (SJ) and field plate (FP) structures and the optimum application voltage range is discussed with the previous experimental data. The specific on-resistance limit of the SJ structure is as same as that of the FP structure and inverse proportional to the cell aspect ratio γSJ and γFP (= drift thickness/lateral cell pitch). The cell aspect...
In this work, layout skills using three dimensional (3D) fish bone, slot, and island patterns to enhance the breakdown voltage of PW/NW junction of lateral MOSFETs is developed. Novel lateral double diffused MOSFETs (LDMOSFET) and Double Diffused Drain MOSFETs (DDDMOSFET) without any high voltage (HV) layer are achieved in a standard 5V low voltage (LV) CMOS technology. From the experiment results,...
We propose a super-junction trench gate MOSFET (SJ TGMOSFET) which is fabricated with a simple p-pillar forming process using deep trench and boron silicate glass (BSG) doping process technologies to reduce the process complexity. The p-pillar region is formed through lateral boron diffusion from BSG film and annealing process after the silicon deep etching. For the SJ TGMOSFET fabricated with BSG...
This paper describes anomalous shifts of an off-state I-V curve that are found in an STI-based LD-PMOS, which includes degradation and recovery of breakdown voltage, increase in leakage current, and subsequent destruction under HCI stressing. Our experimental results suggest that the degradation and the recovery are caused by hot electrons injected into the STI around the bottom corner and the top...
4.5 kV IEGT turn-on loss reduction is experimentally and numerically achieved by employing the proposed simple two step gate drive method without affecting PiN diode reverse recovery performance. It was found that 14% of turn-on loss is reduced only by the simple method. This study determines, for the first time, the optimum gate driving in the two step gate drive which can reduce IEGT turn-on loss...
In this paper, a 1200V novel PiN-diode concept realizing low forward voltage drop (VF), low reverse recovery loss and low leakage current at high temperature over 175°C has been proposed. To realize these above-mentioned characteristics, this concept of 1200V diode design adopts a combination of flat and linear distribution of carrier concentration from anode side to cathode side and reducing injection...
A new TCAD-based approach is used to investigate hot-carrier stress (HCS) effects, especially suited for power devices. Physically-based degradation models are used to determine the interface trap generation at different stress biases and ambient temperatures. Special attention has been given to the high current-voltage regimes, when significant self-heating effects and impact ionization play a relevant...
This paper described the electronic performance of power module packaged high-power AlGaN/GaN high electron mobility transistors (HEMTs) on silicon substrate. Sixteen GaN chips are mounted on one AlN substrate. There are three AlN substrate in one module. Each device is wire-bonded in parallel connection to increase the power rating. Both DC and pulsed current-voltage (ID-VDS) characteristics are...
This paper reports on ultra-high voltage, >15 kV SiC PiN rectifiers exhibiting >95% of the avalanche rating and 115 V/μm. This is one of a few reports on > 15 kV blocking voltages measured on any single semiconductor device, and the highest percentage of the avalanche limit ever reported on devices fabricated on > 100 μm thick SiC epilayers. Excellent stability of on-state voltage drop...
This paper elaborates on the requirements of electricity grids when large amounts of regenerative energies, in particular from wind and solar power plants, have to be integrated. It shows the essential role of advanced power electronics for the de-carbonization of our energy supply.
In this paper, a new rectifier structure in silicon carbide (SiC) is presented for the first time. The proposed structure involves neither Schottky contact nor minor carrier injection via P-N junction. With adjacent P+ areas placed sufficiently close, pinched barrier is formed for rectifier purpose. Numerical simulations are carried out to verify its function, and optimize its performance. Based on...
Symmetric blocking power semiconductor switches require two edge terminations, one for the reverse blocking junction and the other one for the forward blocking junction. In this work, we demonstrated 1100V SiC symmetric blocking edge terminations using orthogonal positive bevel (OPB) termination and a one-zone Junction Termination Extension (JTE). The OPB was formed by orthogonally sawing 45° V-shape...
Three basic intermediate bus architectures are reviewed for electronic power system developers. Salient features for practical system development are then discussed in detail, including power efficiency, regulation, component selection, load cross regulation, and board thermal flux density. The double regulated intermediate bus architecture has the best overall efficiency, regulation, size, and thermal...
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