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In this paper, we presents 20-nm-channel length (Lch) high performance InAs-on-insulator (-OI) MOSFETs on Si substrates with Ni-InGaAs metal source/drain (S/D) employing a new contact resistance reduction technology. The devices provide high maximum on-current (Ion) and maximum transconductance (Gm) of 2.38 mA/µm and 1.95 mS/µm at drain voltage (VD) of 0.5 V. This high performance is attributable...
BEOL-friendly Access Devices (AD) based on Cu-containing MIEC materials[1–4] are shown to be capable of both maintaining and moving rapidly between all the roles necessary for 3D crosspoint memory (un-selected, half-selected, selected(read), and selected(write)). Ultra-low leakage is maintained over hours, recovery dynamics after both write (30–50uA) and read (3–6uA) operations are explored, and read...
3 dimensional (3D) scaling extensibility on epitaxial source drain strain technology toward Fin FET and beyond was discussed in terms of performance, uniformity and reliability. Horizontal sigma shape for the epitaxial strain technology is an attractive alternative for Fin FET and beyond. Its structural and electrical superiority was demonstrated.
We have proposed a retention degradation model based on an oxygen diffusion and percolation path cut mechanism in a filament of TaOx bipolar ReRAM. We have developed a new methodology for quantitating the conductive filament characteristics and have revealed that the retention property of ReRAMs can be explained in terms of filament characteristics, including filament size S, density of oxygen vacancies...
We proposed Bit Cost Scalable (BiCS) technology in 2007 as a three-dimensional memory for the future ultra high density storage devices, which extremely reduce the bit costs by vertically stacking memory arrays with punch and plug process. We've applied it to just NAND flash, which is BiCS Flash memory, and established the mass production technology. Moreover, we can apply the BiCS technology to various...
We studied device and circuit performance and their variability for various design and process parameters using TCAD and an analytical RC model. At the 10nm technology node, σCpara and στpd became greater while σRpara and σIon diminish due to lower ρc. Lg, Hfin, Pf2f, and Pp2p were found to be key parameters for mitigating variability. Increasing Hfin provides a path for further performance and area...
Integrated fan-out wafer-level packaging (InFO-WLP) technology with state-of-the-art quality factor (Q) = 64 in 2.4GHz inductor has been demonstrated for RF systems. For the first time, radio frequency (RF) circuits with InFO-WLP have been fabricated to illustrate how the high Q inductor can be used to dramatically improve performance and power consumption concurrently.
Low density-of-states (DOS) of carriers and higher dielectric constants in III–Vs warrants transistor architecture with better electrostatics than conventional bulk FinFETs [1]. Additionally, the integration of III–V FinFETs on 300mm silicon wafers is a key technological challenge due to the large lattice-mismatch between III–Vs and silicon [2]. This paper presents a statistical variability study...
A novel air gap (AG) structure is integrated into TSV formation to achieve high performance interconnects for 3D stacking of 28nm CMOS devices. When benchmarked against conventional TSVs, the most prominent advantages of this novel TSV structure demonstrated reduced capacitance, minimized TSV-induced stress and, hence, reduced keep-out zone (KOZ) for CMOS devices. Our FEM simulation confirms that...
In this paper, we present a 64nm pitch integration and materials strategy to enable aggressive groundrules and extendibility for multi-node insertions. Exploitation of brightfield entitlements at trench and via lithography enables tight via and bi-directional trench pitch. Setting the same mask metal spacing equal to CPP maximized density scaling and speed of standard cell automation by avoiding cell...
A junctionless (JL) gate-all-around (GAA) nanosheet polycrystalline silicon (poly-Si) 2nm channel thin-film transistor (TFT) has been successfully demonstrated. The sub-threshold swing (SS) of 61 mV/decade has been the record reported to date in JL TFTs, and the Ion/Ioff current ratio is 108. The cumulative distribution in nanosheet 2-nm channel is small. JL-GAA TFTs show a low drain-induced barrier...
We systematically study the channel size dependence of 1/f noise and RTN amplitude in nanowire transistors (NW Tr.) by measuring a large number of samples with various parameters such as NW width (WNW), height (HNW), and number (NNW). For a wide range of Lg, WNW and HNW, the universal line appears in the noise (SId/Id2) - 1/(LgWeff) plot explained by conventional carrier number fluctuations. But,...
This paper reports the first electrical results of self-aligned multigate devices based on an innovative 3D-lithography process. HSQ resist exposition through the Silicon channel allows the formation of self-aligned trenches in a single step. Planar Double-Gate (DG) and Gate-All-Around Silicon Nanowire (GAA Si NW) transistors are fabricated with conformal SiO2/Poly-Si:P gate stack and the first electrical...
For the first time, a novel area-efficient, 12F2 crossbar switch block featuring a bidirectional TaO diode-selected, complementary atom switch (DCAS) with diagonal programming lines has been proposed. The compact BEOL-diode, having a high current rectification ratio of 1.7×102 with Jmax=0.6MA/cm2, enables three-terminal operation of the DCAS, realizing select-transistor-less programming and high off-state...
A 14KB 8T-bitcell SRAM array is demonstrated in 22nm tri-gate CMOS with fine-grain dual-VCC assist techniques. VMIN limiting 8T-bitcell nodes are boosted selectively during read and write to improve overall chip-VMIN. Measurements show 130–270mV lower VMIN with 27–46% lower power at 0.4–1.6GHz for varying amounts of boosting, array activity and voltage regulator efficiency.
We demonstrated record 0.37V minimum operation voltage (Vmin) of 2Mb Silicon-on-Thin-Buried-oxide (SOTB) 6T-SRAM. Thanks to the small variability of SOTB (AVT∼1.3 mVµm) and adaptive back biasing (ABB), Vmin was lowered down to ∼0.4 V regardless of temperature. Both fast access time and small standby leakage were achieved by ABB.
The impact of random telegraph noise on ring oscillator (ROSC) frequency was measured for the first time using an on-chip beat frequency detection system. The proposed differential sensing scheme achieves a high frequency measurement resolution (>0.01%) at a short sampling time (>1µs) allowing efficient collection of RTN induced frequency shifts. Experimental data from a ROSC array fabricated...
We propose for the first time a complete SRAM offer in FDSOI technology, covering low leakage, high speed and low voltage customer requirements, through simple and innovative process/design solutions. Starting from a bulk-design direct porting, we evidenced +50% and +200% Iread at Vdd=1V and 0.6V, respectively vs 28LP bulk. Additionally, −100mV Vmin reduction has been demonstrated with 28FDSOI. Alternative...
For 20nm SoC products, we propose an SRAM macro with low dynamic and leakage power. This is achieved by adopting an interleave word-line and hierarchical bit-line scheme, in which minimum portions of circuits are activated when SRAM is accessed. Measured data confirms that the proposed 128kb SRAM realizes 600 mV operation, 2.1 µW/MHz active power and 82 % leakage power reduction.
Key elements of FDSOI (Fully Depleted Silicon on Insulator) technology as applied to SRAMs are described. Thick- and thin-Bottom Oxide (BOX) variants are discussed. Introduction Fully-depleted transistor technologies, both planar and fin-type, are now in the mainstream [1–4]. They offer unique promise to important circuits such as static RAM cells. Planar fully-depleted devices come in two flavors:...
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