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It is our great pleasure to welcome you to the 2017 installment of the IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) in Taipei, Taiwan. This is the 22nd year of the conference, and we are continuing to push the boundaries of low power technology. This year's symposium continues its long tradition of being the premier forum for presentation of research results and industrial...
System-on-Chip (SoC) designs contain a variety of IP blocks which use multiport memories to improve performance by enabling multiple simultaneous operations in the same memory bank. Conventional 2-read/write 8T dual-port SRAMs (2RW) suffer from read and write disturb issues when both wordlines in one row are activated at the same time. 1-read, 1-write 8T decoupled dual port cells (1R1W) eliminate...
A graphics execution core in 22nm combines SRAM array-assist circuits to lower intrinsic VMIN, retention flops to reduce leakage power during stall periods, and a fully integrated hybrid digital LDO/SCVR regulator to provide a cost-effective means to realize autonomous DVFS under a shared-rail scenario [1–2]. In a conventional design, a conservative voltage guard band (VGB) is added to the nominal...
A fully integrated switched capacitor voltage regulator (SCVR) with on-die high density MIM capacitor, distributed across a 14 KB register file (RF) load is demonstrated in 22 nm tri-gate CMOS. The multi-conversion-ratio SCVR provides a wide output voltage range of 0.45–1 V from a fixed input voltage of 1.225 V. It achieves 63–84% conversion efficiency and supports a maximum load current density of...
Many enterprise and mobile systems must operate within strict power constraints. These systems dynamically trade off performance and power to maximize performance while keeping power within specified limits. In multi-core systems, maximizing the number of active cores within a strict power budget requires minimizing the power per core. Lowering core voltage dramatically reduces power, but compromises...
A 14KB 8T-bitcell SRAM array is demonstrated in 22nm tri-gate CMOS with fine-grain dual-VCC assist techniques. VMIN limiting 8T-bitcell nodes are boosted selectively during read and write to improve overall chip-VMIN. Measurements show 130–270mV lower VMIN with 27–46% lower power at 0.4-1.6GHz for varying amounts of boosting, array activity and voltage regulator efficiency.
A 14KB 8T-bitcell SRAM array is demonstrated in 22nm tri-gate CMOS with fine-grain dual-VCC assist techniques. VMIN limiting 8T-bitcell nodes are boosted selectively during read and write to improve overall chip-VMIN. Measurements show 130–270mV lower VMIN with 27–46% lower power at 0.4–1.6GHz for varying amounts of boosting, array activity and voltage regulator efficiency.
A fully integrated switched capacitor voltage regulator (SCVR) with on-die high density MIM capacitor, distributed across a 14KB register file (RF) load with an area overhead of 3.6% is demonstrated in 22nm tri-gate CMOS. The all-digital, multi-conversion-mode SCVR provides a wide output voltage range of 0.45–1V from a fixed input voltage of 1.225V. It achieves 63–84% conversion efficiency and supports...
High-performance microprocessors and SoCs include multiple embedded memory arrays used as register files and low-level caches that typically share the same supply voltage as the core [1]. The desire for wide voltage range operation to optimize power and performance dictates the need for SRAM arrays that can achieve both high performance and low minimum voltage of operation (VMIN). The 8T bitcell (Fig...
This session brings together specialists from the DfT, DfY and DfR domains that will address key problems together with their solutions for the 14nm node and beyond, dealing with extremely complex chips affected by high defect levels, unpredictable and heterogeneous timing behavior, circuit degradation over time, including extreme situations related with the ultimate CMOS nodes, where all processor...
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