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The current industry trends towards reducing feature size and increasing integration density call for the use of copper (Cu) metallization and low permittivity (low-k) interlayer dielectrics (ILD). Low-k dielectrics are typically characterized by low mechanical strength, low hardness and high porosity (Blaine et al., 2002). The thermal mismatch stresses induced by the manufacturing process pose significant...
This paper investigates the mechanism of the temperature dependence of the Blech product for both the Cu/oxide and Cu/low-k interconnections. Using finite element modeling (FEM), we demonstrate that Blech product should be temperature dependent at high temperature if the inelastic behavior of Cu is considered. This inelastic behavior has not been taken into consideration in the previous works. The...
Leakage and dielectric breakdown of SiO2 are studied for Cu interconnect structures with either stand-alone CoWP or two-layer CoWP+SiN caps. Without a post-CoWP plasma clean, there are many early fails and the dielectric breakdown exhibits bimodal behavior. By adding a plasma clean after CoWP deposition, the early fails can be eliminated and high dielectric breakdown is achieved. The improvement in...
The application of backside emission and laser technique (TIVA/OBIRCH) had been widely used in the semiconductor industry. This paper will discuss the usage of backside laser damage method to aid in this technique on localizing the failure spot. Two applications on backside laser; 1.Memory scramble verification and 2. Yield loss scenario using backside laser to verify the failure hypothesis will also...
The growing applications of microsystem devices in extreme environments have a great impact on the rising importance of their reliability studies. Reliability study in MEMS lacks the availability of methods and tools to analyze them in a quick and efficient way. In this paper, we present a novel approach for reliability analysis in MEMS using worst-case methods. The method facilitates the designers...
Many types of ESD protection devices such as diodes, NFETs, SCRs and RC-triggered power clamps having different failure mechanisms are used in advanced CMOS technologies. Circuit schematic analysis and SEM failure analysis are utilized to clearly predict and identify the failing I/O driver/receiver devices and/or the various ESD protection devices during an ESD event.
In this work, different failure modes and degradation mechanisms of AlInGaN LEDs were studied under different stress conditions. Another aim of this work was to develop a classification criteria of the LEDs based on initial RBL characteristics and enable the manufacturers ensure better reliability standards.
This paper first explains how this algorithm is applied to reject as many suspicious parts as possible and not throwing away any good parts at the same time. The most interesting question for the failure analyst will be answered in the main part: What kind of defects, if any, can be found on the rejected (but functional) chips, that could have an impact on reliability? The failure analysis flow based...
Successful measurements, applying the EBP to the backside of thinned circuitry, using test structures and commercial chips have been demonstrated. In addition to the well known CCVC a new contrast mechanism named space charge coupled voltage contrast (SCCVC) was detected, which strongly increased the EBP signal measured directly on the transistor source or drain regions. Therefore, measurements are...
In this paper it was demonstrated that by applying the classical way of reliability lifetime prediction, the reliability of a product can no longer be guaranteed in some cases and for some failure mechanisms. This is caused by reduced reliability margins under the influence of increasing fields, current and power densities on the one hand, by introduction of new materials and devices on the other...
The measurement of timing and voltage signals inside integrated circuits (IC) is critical to debugging new devices, to failure analysis of advanced devices, validating new IP (intellectual property) in new silicon, etc. E-beam probing (EBP) has been very useful for front side devices for over two decades. For measuring signals below the top metal layers, probe pads are made using a focused ion beam...
In this paper we presented a retrospective on Moore's law, highlighting the salient feature of industry leading 65nm CMOS technology for high performance logic, and highlighted future challenges and approaches to overcome those.
NiSi has replaced CoSi2 as the salicide material for 65 nm technology and beyond mainly due to its low salicide resistance for the narrow line width structures. However, it may bring along unwanted salicidation, resulting in failed transistors. This paper highlights how unwanted salicidation, also known as Ni piping, is successfully identified by physical and electrical failure analysis techniques.
Atomic scale lattice strain measurement using high resolution transmission electron microscopic (HR- TEM) is an important application for semiconductor device characterization. Recent advancement and issues in these areas are discussed. Their potential applications in contemporary sub-45 nm metal-oxide- semiconductor field effect transistor (MOSFET) technology nodes are crucial. Major technical limitation...
After over 10 years of intensive study on high-k dielectric and metal gate electrode to replace silicon based materials (Si02 or SiON gate dielectric and polysilicon gate) in the complementary-metal-oxide-semiconductor (CMOS) application, it was claimed that hafnium based dielectric and metal gate are finally ready to be implemented in 45nm technology and beyond. It was reported that the minority...
Fhis paper is to present a novel methodology to overcome above hardness, and two case study are brought out to demonstrate the application. In our methodology, no any new instrument was needed but only through these already accomplished EFA/PFA equipments. The key consideration to develop such ideas were due to keeping testability and effectiveness in these conventional tools for focusing on the capabilities...
Dynamic optical techniques (light emission and laser stimulation techniques) are routinely used for precise IC defect localization. As device technology is more and more shrinking, developing new techniques for defect localization is becoming a crucial challenge. Dynamic Laser Stimulation (DLS) techniques based on near-infrared laser scanning are used for failure analysis, design debug and time margin...
For the first time, EBIC microscopy is applied for investigations on active polymer devices, OFETs with TPA-Dimethyl and P3HT polymers as active layers. The internal electrical field distributions of these devices are characterized in dependence on biasing conditions. Poole-Frenkel field dependences at source and drain contacts are demonstrated.
The ESD robustness on different device structures and layout parameters of high-voltage (HV) NMOS has been investigated in 40-V CMOS process with silicon verification. It was demonstrated that a specific structure of HV n-type silicon controlled rectifier (HVNSCR) embedded into HV NMOS without N-drift implant in the drain region has the best ESD robustness. Moreover, due to the different current distributions...
PMOS-triggered SCR devices with initial-on function have been proposed to achieve an efficient ESD protection in deep-submicron CMOS technology. The channel length of the embedded PMOS transistor in the PMOS-triggered SCR device dominates the trigger mechanism to govern the trigger voltage, holding voltage, turned-on resistance, second breakdown current, turn-on efficiency, and ESD robustness of the...
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