The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Through Silicon Vias (TSVs) are crucial elements for the reliable operation and the yield of three dimensional integrated circuits (3D ICs). Resistive open defects are a serious concern in TSV structures. In this paper, a post-bond, parallel testing technique is proposed for the detection and location of resistive open defects in TSVs, which is based on easily synthesizable all digital testing circuitry...
In digital logic circuits, unconstrained scan tests are known to evoke much higher switching activity than functional modes. To create test conditions which are as similar as possible to functional modes, today's ATPG tools have knobs to constrain the switching activity of the generated test to a user-defined functional (= lower) level. Two-dimensional system chips (SoCs) and three-dimensional stacked...
Through Silicon VIAs (TSVs) are critical elements in three dimensional integrated circuits (3D ICs). Various defects may occur during their fabrication process, the bonding stage or during their useful lifetime. In this work a testing method is suggested to detect the defects using a post-bond oscillation test scheme. Variations in the output signal's frequency are shown to detect the defects in TSVs...
A study of the impact of metal guard rings on the coupling between two interconnects is presented. The structure is designed over a bulk silicon substrate with epitaxial layer, so the coupling through the substrate is also involved. A lightly doped profile is adopted and is simulated by means of an electromagnetic simulator for various interconnects' distances and different metal layers, assuming...
The case of a defected TSV that has been cracked at the point where an impurity or a void hole originally had been is analyzed in this study. A lumped analytical electrical circuit that models the behavior of this defect is proposed. TSV fault modeling offers assistance in developing new test methods that would improve the reliability of the 3D ICs. The structure is simulated using a commercial 3D...
A study on the coupling through substrate using the case of two square metal pads over bulk silicon substrate with epitaxial layer is presented. A lightly doped profile is adopted and it is simulated by means of an electromagnetic simulator for various pad distances and different metal layers, assuming a 65 nm bulk CMOS technology. Suggestions how to reduce the simulation time when a large number...
Lumped analytical electrical models for partially cracked and void hole defected TSVs are proposed in this paper. Accurately modeling defects may enhance the test methodology and could be vital to improve the quality of TSV-based 3D-ICs. These models were verified by simulations using a commercial 3D resistance, capacitance and inductance extraction tool. The presented simulation results are in close...
This work presents a study on the substrate noise coupling between two interconnects. Two different doping profiles are simulated for various interconnect distances and different metal layers assuming a 65 nm bulk CMOS technology. A proper data analysis methodology is presented, including z and s parameters extraction and de-embedding procedure.
A lumped analytical electrical model for cracked (open fault) TSVs is proposed in this paper. Accurate and reliable fault models can support the test methods for the possible defects and they can be vital to improve the quality of TSV-based 3D-ICs. The model is verified by simulations using a commercial 3D resistance, capacitance and inductance extraction tool. The presented simulation results are...
In this work a 0.5–23GHz three-stage broadband distributed amplifier designed in a standard 0.18μm RF CMOS process is presented. A Darlington connection is used in the design to further increase the bandwidth of the amplifier. Gate and drain transmission lines use small size circular spiral inductors provided by the process. S-parameter simulation results show 8±1dB small signal gain from 0.5 to 20GHz...
A new lumped model fully compatible with SPICE-like simulators is proposed in this work. The model is scalable, technology independent and can unify predict both capacitive and inductive coupling effects. It is validated up to 60 GHz by means of two commercial EM simulators.
A new technique for driving silicon-on-insulator pixel matrixes has been proposed in, which was based on transient charge pumping for evacuating the extra photo-generated charges from the body of the transistor. An 8×8 pixel matrix was designed and fabricated using the above technique. In this paper, the measurement set-up is described and the performance evaluation procedure is given, together with...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.