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A CMOS digital-bits-in/-out Terahertz (THz) nano-radio with 0.57mm2 chip area is presented in this paper. The THz operation and bidirectional transmitter/receiver (TX/RX) architecture lead to radio ultra-miniaturization for Internet-of-Things (IoT) and fîeld-deployable sensor applications. The bidirectional THz radio is configured as a harmonic oscillator in the TX mode or as a super-harmonic super-regenerative...
The advance of CMOS process is still going, but the end is coming into sight. Semiconductor chips with advanced process later than 21nm are so expensive that they are developed only for million selling products. On the other hand, the advanced AI, IoT and big data technologies require more and more computation/communication power with a tightly limited power budget. How we can develop a “Cool chips”...
The following topics are dealt with: neurosynaptic integrated circuit; digital microfluidic biochips; supercomputer; flip-flops; ARM-FPGA; CPU; system-on-chips; vehicle intelligence; convolutional neural networks; silicon-on-insulator; STT-RAM; video signal processing; and CMOS integrated circuit.
The comparison our proposed model and the evaluation of a real accelerator chip appeared that the model is well matched to the real chip when the operational frequency is relatively low. Also, it appears that under the room light with a large inner resistance, the strong reverse bias is effective. With the bright light, a relatively weak reverse bias is advantageous. The improvement of the model for...
In the present study, a look up table (LUT) based approach is used to extract device characteristics of an SOI based UDGMOSFET built in TCAD and imported to Cadence Virtuoso to implement analog circuit blocks. In particular, this study utilizes the custom 14nm UDGMOSFET to build a simple CMOS inverter, a single ended voltage amplifier and a Schmitt Trigger circuit. The circuits are simulated in Cadence...
An optimally designed CMOS Op-Amp has been presented in this article. Opposition concept based harmony Search (OHS) algorithm is applied for obtaining the minimum MOS area of the proposed Op-Amp. The proposed OHS based analog CMOS Op-Amp circuit design has alleviated from the problems of suboptimal convergence and stagnation, unlike Particle Swarm Optimization (PSO) and Harmony Search (HS). The least...
Silicon interposer and bridge is a multi-chip 3D technology that enables high density die-to-die interconnect on a package substrate. It opens a new era for heterogeneous on-package system integration. This paper presents an overview of this packaging architecture and its capabilities from concept to results. The overall components are introduced and discussed including constituent building blocks,...
This paper presents MEMS multi-sensors with low power tunable-gain interface circuit that can be monolithically integrated in the ASIC compatible standard CMOS process. A high gain ultra-low power sustaining TIA amplifier circuit with PLL compactly has been integrated with the resonator-based core sensing structure. The proposed low-power readout circuit adopts Correlated Double Sampling (CDS) to...
Scaling down the complementary metal oxide semiconductor field effect transistors (COMS FET) requires involvement of High K (HK) metal gate technology in sub 45nm nodes. HK enables significant lower leakage at similar effective oxide thickness (EOT) to SiO2 by effective suppression of direct tunneling. However, stress induced leakage current (SILC) and defects in the ultrathin interlayer in HK stack...
In order to improve the semiconductor device performance, decoupled plasma nitridation (DPN) process was used to form the ultra-thin gate oxide film. But we recently found serious residue defect on gate oxide film if we did lithography rework with chemical method. This defect was like a circular-pattern about several-micron in diameter and hard to be removed. The results also showed that the thickness...
In this paper, the Smoluchoski effect will be explained and is further used to understand the physics of the current-voltage (I–V) characteristics of high-k MIM capacitors in mixed-signal CMOS technology application.
CMOS and nano-electromechanical (NEM) hybrid reconfigurable logic (RL) circuits are implemented by using monolithic three-dimensional (M3D) integration process. Their operation and feasibility are discussed based on simulation and experimental results.
Intel® introduced an energy efficient SoC power delivery scheme utilizing fully-integrated high-frequency voltage regulators along the roadmap of Moore's law scaling. From 22nm process to 14nm or even 10nm, circuit blocks shrink and the embedded passives are scaled sequentially in the similar manner. A major challenge in the on-die VR design is to achieve sufficient integration and minimization of...
An improved active-quenching circuit and a linear counting circuit used for a silicon single photon avalanche diode (SPAD) are presented in this paper. The proposed quenching circuit is fast and compact. The linear counting circuit can achieve 10 bit large count range with a small capacitor, which can effectively reduce the area of pixel. Due to the significant advantages of low-cost, compactness...
This paper presents a parallel readout circuit for high density single photon avalanche diode (SPAD) pixel array. Each pixel consists of analog quenching circuit and counting circuit. Column parallel readout method is adopted and every eight columns of array pixel shares one multiplexer where the analog output signals of these pixels are selected to pass it subsequently. After that, the signals will...
Huahong Grace Semiconductor Manufacturing Corporation (HHGrace) is the largest 8 inch wafer fabrication foundry in China with strong expertise in CMOS fabrication processes. By leveraging on the existing matured CMOS process capabilities, HHGrace has successfully developed MEMS platforms using existing equipments coupled with the combination of MEMS special tool sets. HHGrace has demonstrated its...
In this paper, we propose a TFET (Tunneling Field Effect Transistor) PMU (power management unit) of R80515 for ultra-low power. Both the dynamic power and leakage power are evaluated by HSPICE circuit simulation with Verilog-A models. From the simulation, we find the dynamic power of TFET circuits can be reduced by 80% and leakage power reduction can be nearly 30% compared with 130nm CMOS (Complementary...
As semiconductor technology node continuously shrinks, Wet strip process works as a more important role beyond 45m. For RC delay concern, Ultra Low-K material is introduced to BEOL ILD (Interlayer Dielectric). After Trench First Metal Hard Mask All-in-One Etch, ULK film sidewalls are exposed during Wet strip. Wet strip needs to take care of not only no ULK K value shift, but also HM TiN pull back...
LDMOS (Lateral Double-diffused Metal Oxide Semiconductor) is widely used to smart power management IC, which can be attributed to its high operation voltage and high current driving capability. Furthermore, LDMOS is compatible with conventional CMOS processes. It will be much easier for IC foundries to make it by existing process flows. Operating at both a high drain voltage and a high current, LDMOS...
LDMOS (lateral diffused MOS) is an important class of device finding applications in high voltage and smart power management due to their compatibility with the standard CMOS process. However, high operational drain voltage makes LDMOS devices highly vulnerable to the damage caused by hot-carrier injection (HCI). In this paper, the various layout parameters of NLDMOS with shallow trench isolation...
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