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Currently the market and the academic community have required applications of image and video processing with several real-time constraints. In order to seek an alternative design that allows the rapid development of real time image processing systems this paper proposes an unified hardware architecture for some image filtering algorithms in space domain, such as windowing-based operations, which...
The H.264/AVC intra-frame codec is widely used to compress image/video data for applications like Digital Still Camera (DSC), Digital Video Camera (DVC), Television Studio Broadcast, and Surveillance video. Intra-prediction is one of the top 3 compute-intensive processing functions in the H.264/AVC baseline decoder and, therefore, consumes significant number of compute cycles a processor. In this...
In this work we present a real time video processing framework, which can handle high data throughput rates. Contrary to common digital hardware realizations which use several image line long shift register pipelines for direct calculation of 2D neighborhood operations, we suggest an efficient cyclic image line storage structure by using dual port block RAM buffers, which are available in recent FPGAs...
The usage of Cellular Automata (CA) for image processing tasks in self-organizing systems is a well known method, but it is a challenge to process such CAs in an embedded hardware efficiently. CAs present a helpful base for the design of both robust and fast solutions for embedded image processing hardware. Therefore, we have developed a system on a chip called ParCA which is a programmable architecture...
This paper presents a design methodology for hardware/software (HW/SW) architecture design using ESL tools (Electronic System Level). From C++ descriptions, our design flow is able to generate hardware blocks running with a software part and all necessary codes to prototype the HW/SW system on Xilinx FPGAs. Therefore we use assistance of high level synthesis tools (Catapult C Synthesis), logic synthesis...
This paper presents a hardware design for the H.264/AVC Eighth-Pixel Chrominance Interpolation Unit that is a part of the Motion Compensation Unit. The architecture was optimized to reach a high throughput through a balanced pipeline and internal parallelism exploration. The design was described in VHDL and synthesized to a Xilinx Virtex2p FPGA. The best performance results achieve an operation frequency...
Regarding internal memory size, we proposed a new scan method for block-based structure to provide an efficient parametric structure for two Dimensional Discrete Wavelet Transform (2-D DWT). The main challenge in 2-D DWT structure is the amount of internal memory required to produce wavelet coefficients. The previous structures need fixed memory size depend on input frame size, but in proposed architecture,...
Real-time video compression applications such as Digital Video Camera (DVC), Television Studio Broadcast, and Surveillance video utilize the H.264/AVC video encoder in intra-only encoding mode. The H.264/AVC standard supports multiple intra-prediction modes to reduce spatial redundancy in the video frame. The intra-prediction process for a current pixels block requires the reconstructed pixels from...
Object detection is a vital task in several emerging applications, requiring real-time detection frame-rate and low energy consumption for use in embedded and mobile devices. This paper proposes a hardware-based, depth-directed search method for reducing the search space involved in object detection, resulting in significant speed-ups and energy savings. The proposed architecture utilizes the disparity...
This paper presents a new method for accurate skin detection. Skin detection techniques are used in various image and video processing applications, such as image categorization, face detection and tracking and, more recently, in selective image enhancement for digital TV products. The proposed method achieves high accuracy using a combination of color information and pseudo-morphological processing,...
This paper presents some propositions to reduce consuming memory and increase operational frequency of hardware implementation of JPEG-LS algorithm for real time applications. By enhancement in the algorithm and using fast divider, memory has been reduced by 24%. Also, considering the proposed non-stalling pipeline architecture by using forwarding technique to avoid hazards, circuit frequency has...
Control the data flow between device interfaces, processing blocks and memories in a vision system is complex in hardware implementation. In the research, high-level synthesis tool is used to design, implement and test the vision system within the context of required control, synchronization, and parameterization on a processor based platform. In addition, both HLS tools and HDL were used for the...
This paper presents the use of local oriented energy features for real-time object tracking on embedded vision systems. Local oriented energy features are extracted using complex Gabor filters. Filtering is carried out across multiple channels with different frequencies and orientations. The effectiveness of the chosen feature set is tested using a mean-shift tracker. Our experiments show that adding...
The partial reconfigurability of FPGAs allows real-time systems to adapt to changing application requirements. However, the additional time and power needed for partial reconfiguration as well as the sequential reconfiguration process degrade the overall system performance. This is considered as one of the main reasons for restricted use of partial reconfiguration technology. In addition, hardware...
The purpose of this paper is the design of target recognition system based on machine vision. Through the needs analysis of the system, hardware platform and software platform is built on machine vision. The scheme of machine vision based on PXI bus is put forwarded. The VISION module which is the machine vision of Lab VIEW software is introduced. The target (star) of the image acquisition and target...
In view of the increasing demand of recognition system for paper currency number, to develop a type of number recognition system based on CIS and DSP. The hardware is composed of CIS and DSP which control image acquisition and process. The software is composed of image acquisition, character correction and recognition. To recognize character with noise pollution rapidly and accurately, a novel approach...
The current explosion of digital media creates threats towards the security in multimedia data broadcasting. Watermarking technique becomes a prospective solution to this coercion by means of Intellectual Property Right Protection, Authentication and Integrity Verification of digital media. In this paper we introduce an approach that enables us to develop a low power, real time, reliable and secure...
The research presented here is an attempt to use a very basic, low cost and non-specialized microcontroller for image processing tasks. The applications emanating from such an attempt will result in inexpensive face detection, intelligent motion sensors to low cost vehicle counting systems. We have been able to develop a system based on Microchip dsPIC microcontroller that implements edge detection...
This paper proposes a new intra prediction architecture for high resolution applications. The standard intra prediction has a data dependency for the pipelined processing. To enable the pipelined intra prediction architecture, processing order changing methods and additional processing schedulers are proposed. However, previous methods are not considered for the parallel processing which is a key...
Motion estimation plays an important role in inter-frame prediction for the video coding standards such as H.264/AVC, MPEG-2, MPEG-4, VC-1, and so on. Its huge computation complexity, however, makes it difficult to achieve real-time coding for the HDTV1080p. In this paper, we propose a dynamic search range algorithm which reduces about 80% of search points in full search algorithm for the H.264/AVC...
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