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The emergence of networks of many devices in the context of cyber-physical systems motivates novel solutions for communication over random access channels. Currently deployed random access protocols attempt to avoid collisions, and target the performance of a scheduled multiple access system (a strategy known to be only suboptimal from the information-theoretic perspective). In contrast, in this paper,...
Recently, the requirement for non-volatile memory on embedded systems has increased because they can be applied with normally-off and power gating technologies to. However, they have a lower endurance than volatile memories. When data is encoded as a write-reduction code appropriately, the endurance of non-volatile memory can be enhanced by writing the encoded data into the memory. We propose a highly...
Reliability of Network-on-Chip has become a critical problem because of the aggressive technology scaling. A variety of transmission mechanism to tolerant the bit errors has been proposed to achieve the best trade-off between performance and overhead. In this work, a transmission mechanism for NoC based on a novel combination of error detection, error correction, and retransmission is proposed. The...
We study potential enhancement of the read access speed in high-performance solid-state drives (SSDs) by coding, given speed variations across the multiple flash interfaces and assuming occasional local memory failures. Our analysis is based on a queuing model that incorporates both read request failures and node failures. It provides a clear picture on the coding-overhead and read-access-time trade-offs...
In traditional (k, n) threshold secret image sharing (SIS), a secret image is encrypted into n shadow images (also called shares) distributed to n associated participants. The secret image can be recovered by collecting any k or more shadow images, i.e., SIS is loss-tolerant. In SIS research domain, visual cryptography scheme (VCS) also called visual secret sharing (VSS) and Shamir's polynomial-based...
In this study, Layered Low Density Parity Check (LDPC) Decoder algorithm in Error Correction Codes is implemented on FPGA. Firstly, Layered LDPC Decoder algorithm is designed with floating point in MATLAB, then fixed point model is developed. By testing Floating and Fixed point designs, transmitted information that is deformed by AWGN model is corrected by decoding iteratively. After this step, fixed...
Recently, the forward error correction (FEC) codes are gaining popularity in video transmission community because of its capability of recovering lost packets in lossy wireless networks. The state-of-the-art scheme for FEC video transmission are the delay-aware fountain codes (DAF), which combine the ratelessness of fountain codes with the property of video coding. However, DAF assumes that all the...
Scaling of CMOS technology to nanoscale increases soft error rate in memory cells. Both single bit upset and Multiple Cell Upsets (MCUs) causes reliability issues in memory applications. Transient multiple cell upsets (MCUs) are becoming major issues in the reliability of memories exposed to radiation environment and affect large number of cells. Hence to provide fault tolerant memory cells, Error...
Combined (soft-hard) method for decoding block turbo-product codes is proposed in the paper. The method allows leveraging advantages of soft input data usage with the speed of hard-decoding procedure. The main peculiarity of the method is rule-based decoding stage. The proposed approach simplifies calculation procedure and reaches better correction ability than hard-decision decoder. Mathematical...
As solid state drives (SSDs) are gradually replacing hard disk drives, error correction is critical to SSDs since NAND flash has deteriorating reliability over their life span. Existing error correction codes suffer from limited error correction capability or error floor issues. Polar codes are promising for SSDs since they are theoretically proven optimal codes and have good error floor behavior...
NAND flash memory has decreasing storage reliability, as the density or program/erase (P/E) cycle increases. To ensure data integrity, error correction codes (ECCs) are widely employed and typically stored in the out-of-band area (OOB) of flash pages. However, the worst-case oriented ECC is largely under-utilized in the early stage (small P/E cycles), and the required ECC redundancy may be too large...
With a development of process technology, a memory density has been increased. However, a smaller feature size makes the memory susceptible to soft errors. For reliability enhancement, ECC with single bit error correction and double bit error detection is widely used. As multiple bit cell upset become dominant, there is a need for stronger ECC. ECC such as RS or BCH code requires significantly large...
As CMOS technology scales down, multiple cell upsets (MCUs) caused by a single radiation particle have become one of the most challenging reliability issues for memories in space applications. In general, bits affected by MCUs are usually physically close. Error correction codes (ECCs) are commonly used to protect memory against MCUs. Recently, Matrix-based codes are an interesting option due to their...
Many researchers have analyzed the error correction capability of LDPC codes for iterative decoding algorithms. However, it is difficult to show the error correction capability of LDPC codes for iterative decoding algorithms based on belief propagation theoretically. Chilappagari et al. reported the error correction capability of column-weight-three regular LDPC codes under the Gallager A algorithm...
Much attention has been paid to higher frequency (HF) radio communication providing large capacity. As well, maintaining its communication quality is one of the crucial issues, and diversity approaches should be effective ways in terms of physical layer. Differential Space-Time Block Coding (DSTBC), which is a spatial diversity strategy, has robustness against phase noise serious in a HF band. Employing...
We investigate a synchronization method for channels that are impaired by insertion, deletion, and substitution (IDS) errors and include outer low-density parity-check (LDPC) codes with error-correction capabilities and inner marker codes for synchronization. We improve synchronization using fixed-symbols, and evaluate the achievable rate by a specific fixed-symbol assignment. We demonstrate via...
An application of convolutional codes is the burst error correcting, and the terminated Berlekamp-Preparata convolutional codes are the suboptimal phased burst error correcting codes. This paper presents a decoding method of tail-biting Berlekamp-Preparata convolutional codes that based on tail-biting technology, which can correct the final m block errors without m block termination check data within...
Symbol-pair read channels output overlapping pairs of symbols in storage applications. Pair distance and pair error are used in the channels. In this paper, we discuss the error-trapping decoding for cyclic codes over symbol-pair read channels. By putting some restrictions on the correctable pair error patterns, we discuss a new error-trapping decoding algorithm over the channels and show a circuitry...
This paper presents the new method permuted decoding BCH based on a norm of syndrome. This approach allows correction of the random error and burst error simultaneously. This method is combined with a cyclotomic permutation to reduce the complexity of the decoder. The proposed method reaches the gain coding to 5dB at BER = 10-4 on the flat fading Rayleigh channel compared with the algebraic method.
In order to relieve reliability problem caused by technology scaling, LDPC codes have been widely applied in flash memories to provide high error correction capability. However, LDPC read performance slowdown along with data retention largely weakens the access speed advantage of flash memories. This paper considers to apply the concept of refresh, that were used for flash lifetime improvement, to...
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