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Recently, a new type of product-like codes, known as half-product codes, has been studied for OTN applications. Binary half-product codes show excellent bit-error-rate performance under iterative hard-decision decoding in the waterfall region. To further improve the performance in the error floor region, a novel post-processor algorithm is proposed that relies on conditional bit flipping. For a class...
In this paper, we solve the optimizing problem of designing Low-Density Parity Check codes for two parallel erasure links based on the known SDP approach. We show that our reformulation is suitable for this optimizing problem. Our results show that the optimal rate code design problem is a good way and worth-mentioning tool. One can extend our work to the other area.
This paper proposes a low-complexity high performance soft-in hard-out decoding algorithm for Reed-Solomon (RS) codes. The Guruswami-Sudan (GS) algebraic list decoding algorithm can correct errors beyond half the distance bound by performing a curve-fitting decoding process. However, its extra error-correction capability is exchanged with a high computational cost which is dominated by the interpolation...
This paper presents the new method permuted decoding BCH based on a norm of syndrome. This approach allows correction of the random error and burst error simultaneously. This method is combined with a cyclotomic permutation to reduce the complexity of the decoder. The proposed method reaches the gain coding to 5dB at BER = 10-4 on the flat fading Rayleigh channel compared with the algebraic method.
Flash memory development through technology scaling and bit density has significant impact on the reliability of flash cells. Hence strong error correction code (ECC) schemes are highly recommended. With a strong error correction capability, low-density-parity code (LDPC) is now applied for the state-of-the-art flash memory. However, LDPC has long decoding latency when the raw bit error rates (RBER)...
LDPC convolutional codes (LDPC-CC) are a family of error-correcting codes (ECC) used in digital communication systems like the IEEE 1901 standard. High throughput and low complexity hardware architectures were designed for real time systems. In this article we demonstrate that an efficient selection of the message passing (MP) algorithm for LDPC-CC decoding improves the architecture features of related...
Product codes are a concatenated error-correction scheme that has been often considered for applications requiring very low bit-error rates, which demand that the error floor be decreased as much as possible. In this work, we consider product codes constructed from polynomial algebraic codes, and propose a novel low-complexity post-processing technique that is able to improve the error-correction...
Most of the turbo decoding stopping criteria assume perfect channel reliability available at the receiver since they require a threshold based on signal-to-noise ratio (SNR) information. However, operational environments can vary according to frame sizes, code structures and channel reliability requirements, further aggravating the difficulty in threshold determination and convergence or non-convergence...
In this paper, we perform a simulated fault injection reliability assessment of memory centric flooded LDPC decoders affected by probabilistic storage errors. We investigate the error correction capability in terms of Frame Error Rate (FER) of faulty flooded Min-Sum decoder, under Binary Additive White Gaussian Noise (BiAWGN) channel model. We have injected all the memories, as well as only the memories...
We propose and design a lattice coded physical- layer network coding (PNC) over a finite complex number field Z[ω]/ξZ[ω] in a two-way relay channel (TWRC). In our design, we construct the lattice codes from an irregular repeat- accumulate (IRA) code over GF(q). A randomly generated coset is employed to our scheme to ensure that the codes exhibit permutation invariance and...
We propose a new low-density parity-check (LDPC) coded binary physical-layer network coding (PNC) scheme for Gaussian two-way relay channels. In this scheme, we introduce a bit mapper between the LDPC encoder and the modulator, which considers the unequal error protections brought by the high order PSK modulations. We add a new bipartite sub-channel graph consisting of sub-channels and variable nodes...
Because of their excellent error correction performance, Low-Density Parity Check Codes (LDPC) have become the most widely used technique for forward error correction in almost all modern communications applications. This paper introduces an FPGA implementation of a partial parallel, flexible LDPC decoder based on the Min-Sum decoding algorithm. The suggested architecture uses a combination of unicast...
This contribution considers the word error rate (WER) performance of a concatenated coding scheme in the presence of impulsive noise (IN), which is modeled as gated white Gaussian noise, with on- and off-times governed by a 2-state Markov model. The scheme consists of a Reed-Solomon (RS) outer code and a low-density parity-check (LDPC) inner code, which are separated by a block interleaver with finite...
Due to high error correcting capability turbo coding is highly used in digital communication systems. In this article a new design of turbo decoder with reduced dynamic power dissipation is presented. In this modified decoder, standard cell based design using pipeline logarithm-maximum a posterior (Log-MAP) algorithm with clock gating and variable number of iteration is used to reduce the area and...
A forward error correction scheme for asynchronous sensor communication is proposed, where a continuous-time sparse waveform signal is asynchronously sampled and communicated over a noisy channel via Q-ary frequency-shift keying. The presented concatenated code employs outer systematic convolutional codes and inner embedded marker codes, which effectively preserve the timing information along with...
In this paper, we demonstrate the performance of low complexity soft interference cancellation minimum mean-squared error (SIC-MMSE) detection method for a turbo coded multiple-input multiple-output (MIMO) system with joint iterative detection and decoding (JIDD) principle. The main computational burden of SIC-MMSE detector lies in the multiple inverse operation of the filtering process and maximum...
One of the most important solutions for spectrum shortage, expected by 2020, is wireless networks with super density, which is also expected to provide significant economic impacts. This paper proposes decoding scheme with practical analysis for massive number of users in super-dense wireless networks involving two multiway relays (SD-MWMR). The practicality is viewed from the point of finite-length...
With the advent of the space age, deep space exploration increasingly has become an important strategic task for human beings. To carry out space exploration, it is necessary to launch many space detectors with a variety of purposes, so that it requires establishing effective communication between the detector, and between the detectors and the Earth, that is to carry out deep space communication...
LDPC block codes (LDPC-BCs) have attracted great interests in recent years by highly parallel computation and good bit-error-rate performance, and one of the decoder implementation issues is high routing complexity. LDPC convolutional codes (LDPC-CCs) not only release routing complexity but also are natural to dynamic length of data frame. Thus, the codes are very suitable for video stream and pre-5G...
This paper proposes a QC-LDPC partial parallel architecture that implements a hard decision message passing algorithm based on Gallager-B decoding. The proposed architecture uses an optimized variable node unit, with adaptive threshold, suitable for irregular LDPC codes. We present implementation results for WiMAX rate 1/2 code for FPGA technology. These indicate a cost reduction of 2.5x in logic,...
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