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Security issue occupies an important part in all communication system and especially for new generation networks. Among these networks, we find Delay Tolerant Mobile Networks (DTMNs) which are a class of useful but challenging networks. Combining Network Coding (NC) and clustering for routing in such networks gives more efficiency and copes with routing reliability problem among large scale networks...
Hardware Trojan Horses (HTH) are a serious threat to semiconductor industry with significant economic impact. We introduced in [10] a method called “encoded circuit”, which both prevents and detects HTH. We achieved this goal using Linear Complementary Dual (LCD) codes. In this paper, we achieve a lower overhead and a better tunability by using a Linear Complementary Pair (LCP) of codes, which are...
This paper demonstrates the Flash ADC which is constructed using digital 3-input cross coupled NAND gates. These cross coupled configuration of NAND gates form a comparator of flash ADC. It is latch comparator which operates on single phase clock Φ. The output of comparator is thermometer code. An encoder is constructed that encodes the thermometer code to binary as output of comparator. The design...
Network anti-virus (AV) solutions are the first line of defense against malicious software. Traditional proxy-based network anti-virus solutions with store-scan-forward techniques decrease network performance and consume massive amounts of memory. Therefore, traditional solutions are not easily adaptable for Network Function Virtualization (NFV). This paper details the work on a novel virus scanning...
Reversible logic has received great importance in the recent years because of its feature of reduction in power dissipation. It finds applications in low power digital designs, quantum computing, nanotechnology, DNA computing etc. Large number of researches are currently ongoing on sequential and combinational circuits using reversible logic. Decoders are one of the most important circuits used in...
RAID schemes have been in use for hard disk drives to provide improved performance or fault tolerance. RAID schemes, particularly RAID 2 and higher comprise of striping and adding parity. For solid state drives (SSDs), to combat die failures, schemes like RAID 5 and RAID 6 are effective. The idea is to have block level striping with distributed parity to provide data recovery in case of single or...
The quaternary logic system has evolved from and closely related to binary logic system. The logic is capable of handling both quaternary and coupled binary inputs, where binary operands are coupled in pairs to form quaternary entities. A set of operators capable of handling both coupled-binary and ordinary inputs are used. To demonstrate the functionality of this novel logic scheme, some useful logic...
A power optimized communication system is proposed in this paper with clock gating technique. The encoder decoder block and the converter circuits are designed using clock gating for power optimization without degrading the system performance. Unwanted switching activities can be much reduced by using clock gating techniques and power saving can be done. Negative latch has been used to generate the...
Most of the power dissipation in SRAMs is due to the leakage and it is approximately 40% of total power dissipation. The leakage power increases as we move towards the technology scaling unless effectively optimized circuit is introduced to keep the leakage under control. In this paper we report on the optimization of a row decoder in terms of power and area. The row decoder is designed using three...
As the conventional irreversible logic dissipates power for losing bits of information, computing engines has to be designed that do not require energy dissipation but only if computation is done logically reversible. Hence, research on reversible logic has been extensively increased now-a-days for its application in Quantum Computing, nanotechnology, QCA and Low power VLSI etc. In this paper, we...
In this paper an 8B/10B encoder and 10B/8B decoder is implemented which are widely used in high speed applications. In this paper we have used NAND/NOR gate instead of AND/OR gate used in earlier work. We calculated on-chip and hierarchy power for two frequencies (i.e. 20 MHz and 200 MHz) for both encoder and decoder using AND/OR gate and encoder and decoder using NAND/NOR gate. Using NAND/NOR gate...
NAND flash memory has been dominantly used in consumer electronic products ranging from hand-held phones to personal computers. However, the stored data in NAND flash memory is subject to several impairments such as Random Telegraph Noise (RTN), Cell-to-Cell Interference (CCI) and Data Retention Effect over time. In this paper, we focus on the RTN effect over flash memory cells which becomes even...
With the advancement in technology and type of usage of the electronics devices in different applications, demands huge size memories to store or process the data. Typically Static Random Access Memory (SRAM) cells are used due to its high speed access characteristics. With the exponential increase in the size of the memory, the power consumed by the memory cells are also increasing exponentially...
A novel design on faster processing of DNA sequences base on pipelined structure has been presented in this paper. The focus of this paper is to design and develop the hardware architecture to meet the requirement of such processing. In the proposed architecture, instead of comparing the whole DNA search string at once, the entire comparison process is split into four phases using four-stage pipeline...
Quasi-cyclic low-density parity-check (QC-LDPC) codes are used in numerous digital communication and storage systems. Layered LDPC decoding converges faster. To further increase the throughput, multiple block rows of the QC parity check matrix can be included in a layer. However, the maximum achievable clock frequency of the prior multi-block-row layered decoder is limited by the long critical path...
Energy efficient and low power circuit designing has become challenging for many years. Now a day in Modern 1C designing, SRAM design somewhat significant because it will occupy more space on a die and consumes large fraction of energy of the chip. Scaling of conventional CMOS circuit leads to have short channel effects due to which, effect such as drain induced barrier lowering, hot electron effect,...
Substantial imperfections in carbon nanotube (CNT) field-effect transistors (CNFETs) are one key obstacle to the demonstration of large-scale CNFET circuits. In this paper, we first categorize transistors based on the impact of resizing on yield improvement and delay penalty for logic circuits. Then we propose an approach to size transistors in different categories by using redundant CNTs to improve...
This study aims to understand the differences of the reading processes between AND gate and OR gate among experienced learners. Thirty-one male computer science students participated in the study with an average age of 18±0.84 years old from a vocational high school. Each participant answered two inference questions on 2-input AND gate and 2-input OR gate while an eye tracker recorded the participants'...
Memory is the fundamental building block of any digital system. Most of the portable devices used today incorporate SRAM arrays which are vital memory elements. The significant role of reversible logic in designing such circuits is to reduce or completely eliminate power dissipation. According to survey, only few design methodologies have been proposed for the SRAM array and to the best of our knowledge,...
In this paper, an application-specific instruction-set processor (ASIP) implementation for interpolation operation for high efficiency video coding (HEVC) decoders is proposed. HEVC is a new video compression standard that has higher compression efficiency than the previous ones. The proposed ASIP is implemented on the XRC_D2MR processor by augmenting the instruction set architecture in Xtensa Tensilica...
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