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Convolutional encoder is widely applied in lots of wireless communication standards including 3G/4G mobile communications, DVB (Digital Video Broadcasting), IoT(Internet of Things) transmissions and so on. Therefore multi-standard Viterbi decoder design for the above receivers is a hot issue. In this paper, a reconfigurable high performance Viterbi decoder design is proposed for LTE, WiMAX, CDMA2000,...
Flash memories are gaining prominence for utilizing in large scale data centers (DCs) due to their high memory density, low power consumption and heat dissipation, and high access speed characteristics. The rate of degradation for a flash memory is largely affected by the amount and frequency of the erase/write operations, which is a challenge in the DC context that serves dynamically changing workloads...
In this invited paper, we describe a rate-adaptive FEC scheme based on LDPC codes together with its software reconfigurable unified FPGA architecture. By FPGA emulation, we demonstrate that this class of rate-adaptive LDPC codes based on shortening with an overhead from 25% to 42.9% provides a coding gain ranging from 13.08 dB to 14.28 dB at a post-FEC BER of 10−15 for BPSK transmission. In addition,...
Automatic hand detection and accurate hand pose estimation from depth data in real system are challenging and vital tasks for human-computer interaction. In this paper, we introduce a Convolutional Neural Network (CNN) as Deep learning regression framework while employing an embedding denoising auto-encoder in the bottom layer of the network to learn latent representation of hand pose and account...
Detecting hand-object interactions is a challenging problem with many applications in the human-computer interaction domain. We present a real-time method that automatically detects hand-object interactions in RGBD sensor data and tracks the object's rigid pose over time. The detection is performed using a fully convolutional neural network, which is purposefully trained to discern the relationship...
This paper presents a fully pipelined layered decoder architecture for IEEE 802.11 n/ac/ax LDPC codes, free of idle cycles. Several decoder architectures for such codes have emerged in the literature featuring throughputs in the multi- Gbps range. The proposed architecture surpasses the highest reported throughput for IEEE 802.11 n/ac/ax LDPC codes. This is achieved 1) algorithmically, by implementing...
Hybrid digital-analog (HDA) architectures have been widely developed for efficient digital transmission of analog speech, audio or video data. By considering the advantage of both digital and analog components, HDA systems gain better performances than purely analog and digital schemes in a wide range of channel conditions. However, HDA systems described in previous works are mostly designed for continuous-valued...
This work presents the first integration of a message-passing detector (MPD) and a polar decoder. A soft-output MPD, which is essential to approach the channel capacity, is first proposed. Compared to the state-of-the-art design, the proposed MPD achieves a 6.9x higher throughput with 49% lower energy, despite the soft outputs. The proposed polar decoder achieves a 1.35x higher throughput with comparable...
This paper presents a Non-Binary LDPC decoder with information throughput of 2.267Gbps and power consumption of 212.4mW, yielding an energy efficiency of 93.7pJ/b, implemented in a 40nm CMOS technology. The employed code is long and high-rate without degree-2 variable nodes, resulting in a low error floor. A dual decoding algorithm scheme alleviates the computational complexity of decoding, realized...
Recent work has employed joint typicality encoding and decoding of nested linear code ensembles to generalize the compute-forward strategy to discrete memoryless multiple-access channels (MACs). An appealing feature of these nested linear code ensembles is that the coding strategies and error probability bounds are conceptually similar to classical techniques for random i.i.d. code ensembles. In this...
Highly reliable data compression technique. Flash Reliability Boost Huffman coding (FRBH) is proposed for TLC NAND Flash memory. By decreasing the write data size and optimizing the memory cell Vth distribution at the same time, FRBH decreases data-retention errors by 92% and increases data-retention time by over 2900 times.
Semantic segmentation is a task that covers most of the perception needs of intelligent vehicles in an unified way. ConvNets excel at this task, as they can be trained end-to-end to accurately classify multiple object categories in an image at the pixel level. However, current approaches normally involve complex architectures that are expensive in terms of computational resources and are not feasible...
Path metric sorting unit of successive cancellation list (SCL) decoders for polar codes is the main concern in this paper. After reviewing existing sorting units in SCL decoders, we propose 2 new sorting schemes namely quick select (QS) based selection algorithm and simplified bitonic sorter (SBT), which exploit the special data dependency of path metrics in log-likelihood ratio based SCL decoding...
Recently, the requirement for non-volatile memory on embedded systems has increased because they can be applied with normally-off and power gating technologies to. However, they have a lower endurance than volatile memories. When data is encoded as a write-reduction code appropriately, the endurance of non-volatile memory can be enhanced by writing the encoded data into the memory. We propose a highly...
Space-time trellis codes (STTCs) combine channel coding and multiple-input multiple-output (MIMO) techniques to provide coding and diversity gains for wireless communication systems. The decoding complexity is extremely high because of the high density of branch metric calculations. Thus, this study presents a state-purging mechanism based on the T-algorithm to reduce the computational complexity...
5-th generation mobile networks aim the peak data rates in excess of few Gbs, which may appear to be challenging to achieve due to the existence of some blocks such as the turbo decoder. In fact, the interleaver is known to be a major challenging part of the turbo decoder due to its need to the parallel interleaved memory access. LTE uses Quadratic Permutation Polynomial (QPP) interleaver, which makes...
Named Data Networking (NDN), a revolution of the IP architecture, provides an information-centric paradigm to transmit video traffic which occupies most of the Internet traffic. However, the data caching schemes exploited by the current NDN can easily result in the unfair distribution of cache space, which is not suitable for performance isolation when there are multiple network users and the cache...
This paper proposes a new architecture Deep Convolutional and Recurrent writer (DCRW) for image generation by adapting the deep Recurrent attentive writer (DRAW) architecture which is a sequential variational auto-encoder with a sequential attention mechanism for image generation. The main difference between DRAW and DCRW is that in DCRW we have replaced RNN in encoder with CNN and after replacement...
In vehicular communication protocol stacks, received messages may not always be decoded successfully due to the complexity of the decoding functions, the uncertainty of the communication load and the limited computation resources. Even worse, an improper implementation of the protocol stack may cause an unfair data age distribution among all the communicating vehicles (the receiving bias problem)...
Traditionally, DFT patterns exacerbate dynamic power consumption in large ASICs. At-speed scan and memory tests are sensitive to voltage droop and peak current because the power grid is designed for functional power viruses (maximum workload applications) whose power consumption is much lower than DFT patterns. Our goal in this work is to ensure that the quality of test is not compromised while power...
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