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The scaling down of semiconductor technology in FPGA increases the soft errors due to radiation effects in space. To address this technological challenge a novel coding technique, Counter Matrix Code (CMC) is proposed to protect the SRAM based FPGA's configuration memories (FCM) against radiation induced Multiple Bit Upsets (MBU) with Low cost and maximum correction capability. The proposed CMC is...
In this article the first complete 1,090 MHz SSR receiving and precision time of arrival (TOA) estimation station field programmable gate array (FPGA) implementation and its analog electronic front-end is presented. The station is designed for local area multilateration (LAM), wide area multilateration (WAM) and automatic dependent surveillance-broadcast (ADS-B) systems. Furthermore it's fully international...
Data conversion operations are important and essential part of floating point units in a processor and typical instructions include conversion between various precisions, integer to floating point and vice versa, floating point to fixed point and vice versa etc. Besides few processors have instructions to round and truncate data, sign injections, move data between co-processors registers and general...
A high-speed non-binary LDPC decoder based on Trellis Min-Max algorithm with layered schedule is presented. The proposed approach compresses the check-node output messages into a reduced set, decreasing the number of messages sent to the variable node. Additionally, the memory resources from the layered architecture are reduced. The proposed decoder was implemented for the (2304,2048) NB-LDPC code...
In this work, our focus is on study and analysis of various IO standards at different temperatures. Virtex-6 is 40-nm FPGA and Kintex7 is 28-nm FPGA on which we implement our circuit to re-assure power reduction in sequential circuit. We have calculated power dissipation of different IO standards and analysed its power. The percentage of reduction in power dissipation for 28-nm FPGA is 65.56% with...
Modern speech recognition applications are heading towards embedded systems and hand-held devices. Distributed Speech Recognition (DSR) system architecture emerged to address this kind of applications. Most of the existing implementations of this system are presented in software fashion, with little consideration to the end product platform in which the system will be deployed. In this paper, an optimized...
Low cost and low power scalar embedded processors can issue only a single instruction per cycle which results in longer execution time for applications and consequently lower energy efficiency. Superscalar processor that can issue multiple instructions per cycle are more energy efficient than scalar processors, however, they consume more power which is severely limited in embedded systems that operate...
This paper presents the design and evaluation of a flexible UHF RFID testbed, which is intended to be used for developing real time localization systems. It is based on an off the shelf software defined radio platform, i.e. the National Instruments USRP-2922. Special requirements for a localization algorithm based on a superimposed Direct Sequence-Spread Spectrum signal which is currently under active...
Aiming at the problems in G.SHDSL application and main methods of building G.SHDSL system, this paper describes the characteristics of G.SHDSL access technology, and designs G.SHDSL signal reconfigurable system based on FPGA because of its reprogrammable ability and strong flexibility, which improves flexibility and capacity of reuse of the G.SHDSL reconfigurable system, and greatly reduces the cost...
The reduced pin-count test (RPCT) has been proposed for testing cost reduction in various scenarios like scan, test compression and multi-site test. In this paper, we propose a new RPCT technique in which several digital signals are combined into a single multi-valued logic (MVL) signal. Mixed-signal components, digital-to-analog and analogto- digital converters, are used to compress the tester channels...
An implementation of chaotic encoder-decoder on FPGA will be proposed in this paper. Overflow non-linearity by using 2's complement number in digital filter causes the phenomenon called "Chaos" in digital filter. An 1ER filter can be used to chaotic encoder while an FIR filter is used to chaotic decoder. Filter coefficients of both encoder and decoder can be compared to the secret key in...
The potential advantages of optical CDMA (OCDMA) over other multi access techniques attracted considerable interest over the past decade. All-optical implementations of OCDMA are often considered to be too complex to implement especially for cost-sensitive applications. On the other hand, electronic realization of OCDMA encoders/decoders are more cost effective but its throughput is restricted by...
Current studies about decoding Fast protocol in the FPGA platform are always implemented using serial communication technique and for some certain Fast Templates. This paper presents the FPGA hardware design of accelerating the decoding process in parallel and cutting down the cost of changing Fast Templates with flexible decoders. The complete system has been simulated and tested in SystemC Platform.
Wireless communication systems are dense compositions of signal processing and VLSI technologies. Due to increase in demand of higher data rate and better quality of services, VLSI design and implementation method for wireless communication becomes more challenging. Multiple-input and multiple-output (MIMO) technique is rapidly increasing in the last decade which provides higher throughput at no additional...
The additional operation of retrieval of the cover image at the decoder is necessary for lossless watermarking system. Taking into account this major issue, efficient implementation of reversible image watermarking needs to be addressed. This can be solved using hardware implementation. This paper focus on the digital design with pipelined architecture of reversible watermarking algorithm based on...
Many varied domain experts use Lab VIEW as a graphical system design tool to implement DSP algorithms on myriad target architectures. In this paper, we introduce the latest LabVIEW FPGA compiler that enables domain experts with minimum hardware knowledge to quickly implement, deploy, and verify their domain-specific applications on FPGA hardware. We present two compiler techniques that we use to 1)...
Design and implementation of signal processing and synchronization algorithms for digital receivers are challenging tasks, especially concerning the verification phase that must cover as many functional tests as possible. This paper discloses the entire internal architecture of the receive chain of the ETSI DVB-S2 digital satellite communication standard and the methodology used for implementing it...
LDPC (Low Density Parity Check) is a channel coding technique is used to correct errors so that the validity of a data transmission on the noise transmission channel guaranteed for accuracy. LDPC is suitable for applications that require a large bandwidth, high reliability, and high noise channel like DVB-S2 (Digital Video Broadcast-Satellite) application. Despite the high level of complexity, LDPC...
A demonstration of FPGA-based 3840×2160 UHDTV (Ultra-high definition TV) H.264 video decoding and displaying system is proposed in this paper. The proposed system can decode and display 3840×2160 video by two Altera Stratix III DE3 FPGA boards, which are connected together with each other by HSTC cable. Video processing system requires high memory bandwidth. This paper locate decoder module and display...
This paper demonstrates a clockless stochastic low-density parity-check (LDPC) decoder implemented on a Field-Programmable Gate Array (FPGA). Stochastic computing reduces the wiring complexity necessary for decoding by replacing operations such as multiplication and division with simple logic gates and serial processing. Clockless decoding increases the throughput of the decoder by eliminating the...
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