The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Spinal codes are a recently proposed capacity-achieving rateless code. While hardware encoding of spinal codes is straightforward, the design of an efficient, high-speed hardware decoder poses significant challenges. We present the first such decoder. By relaxing data dependencies inherent in the classic M-algorithm decoder, we obtain area and throughput competitive with 3GPP turbo codes as well as...
NHK (Japan Broadcasting Corporation) is conducting research on the next generation of digital terrestrial broadcasting system to enable large-volume content services such as UHDTV (ultra-high-definition television). In our previous study, we proposed spatially coupled low density parity check (SC-LDPC) codes for broadcasting. The lengths of these codes can be easily extended and are expected to have...
Current control flow integrity (CFI) enforcement approaches either require instrumenting application executables and even shared libraries, or are unable to defend against sophisticated attacks due to relaxed security policies, or both, many of them also incur high runtime overhead. This paper observes that the main obstacle of providing transparent and strong defense against sophisticated adversaries...
This work presents the design of a Morse decoder implemented using fourteen different architectures described in Verilog. All designs are synthesized in FPGA and ASIC, using Xilinx ISE and Vivado for the former and Leonardo Spectrum and Design Compiler for the latter. The performance and resource requirements after synthesis of each architecture are compared to gain insight on the impact caused by...
This paper proposes an area efficient and low power Reed-Solomon (RS) decoder. The proposed decoder is designed using eight stage arithmetic pipelined architecture. The pipelined architecture of RS decoder performs the detection of error locator from the input stream and computes the error magnitude polynomial using the Berleykamp Massey's algorithm. The evaluation of error locator and computation...
LDPC convolutional codes (LDPC-CC) are a family of error-correcting codes (ECC) used in digital communication systems like the IEEE 1901 standard. High throughput and low complexity hardware architectures were designed for real time systems. In this article we demonstrate that an efficient selection of the message passing (MP) algorithm for LDPC-CC decoding improves the architecture features of related...
This paper investigates the performance of the BCH encoder and decoder for different error-correcting capabilities. The focus is on BCH codes of length 255. The motivation for this research is a project where data symbols of this length are transmitted over an error-prone wireless channel. The paper presents a mathematical introduction into encoding for cyclic codes and decoding of the BCH code. The...
For polar codes, cyclic redundancy check (CRC)-aided successive cancellation list (CA-SCL) decoder has attracted increasing attention from both academia and industry. In this paper, a hardware efficient and low-latency CA-SCL polar decoder based on distributed sorting is first proposed. For path metric (PM) sorting of each level, a distributed sorting (DS) algorithm is proposed to reduce the comparison...
The ability of ultra-low latency to process market data feed is the premise and foundation for a today's trading system to grab the instant trading profits. The market data feed containing up-to-date information on market changes is multicasted real-timely from financial exchanges to market participants, usually in the form of financial information exchange (FIX) Adapted for STreaming (FAST) protocol...
In recent years, there has been a large push in the U.S. Department of Defense (DoD) to more rapidly respond and adapt to changing technology advancements and emerging threats. Nowhere is an accelerated pace of innovation more needed than in the airborne tactical domain where the predominant communication system, Link 16, has been in use for over 40 years. Airborne tactical systems are often stove-piped,...
Polar codes are a new class of block codes with an explicit construction that provably achieve the capacity of various communications channels, even with the low-complexity successive-cancellation (SC) decoding algorithm. Yet, the more complex successive-cancellation list (SCL) decoding algorithm is gathering more attention lately as it significantly improves the error-correction performance of short-to...
A low-power and real-time hidden Markov model (HMM) accelerator is proposed for gesture user interfaces on wearable smart devices. HMM algorithm is widely used for sequence recognitions such as speech recognition and gesture recognition due to its best-in-class recognition accuracy. However, the HMM algorithm incorporates high computational complexity and requires massive memory bandwidth for sequence...
Selection cooperation is a preferable cooperative scheme for wireless sensor networks (WSNs) for its simplification and easy implementation. In this paper, we present a selection cooperation experimental platform (CEP) based on IEEE 802.15.4 WSNs using cheap radios. This work concentrates on employing the lightweight selection cooperation protocol (LSCP) with feedback to govern the cooperation between...
Fractional pixel interpolation for motion compensation is considered among the most computational consuming areas in High Efficiency Video Coding (HEVC). An efficient design and optimized hardware implementation for HEVC motion compensation are presented. This architecture is implemented for 8K HEVC decoder. A new scaling factor for interpolation filter and a modified number of Luma filter taps are...
Security places an important role in communication applications for secure data transfers. Image Steganography is one of the most reliable technique in encryption and decryption of an image (hidden) inside other image (cover) such way that only cover image is visible. In this paper frequency domain Image Steganography using DWT and Modified LSB technique is proposed. The proposed approach uses DWT...
In this paper authors proposed a secured Digital Biometric based watermarking algorithm and its hardware realization by means of Field Programmable Gate Array (FPGA). The scheme focuses on the Graph Based Visual Saliency (GBVS) technique. Biometric watermarking has been introduced for validity and ultimate security of a digital media. Biometric information which is basically fingerprint is being hidden...
In this paper, a hardware-efficient folded SC polar decoder based on k-segment decomposition is first proposed. The proposed k-segment scheme employs (k – 1) N1/k-bit decoders to implement the original N-bit decoder, and reduces the number of mixed-nodes from (N – 1) to (k ă 1)( N1/k – 1) with slightly increased latency. In addition, pipelining technique, partial parallel processing, and pre-computation...
Associative Memories (AM) are storage devices that allow addressing content from part of it, in opposition of classical index-based memories. This property makes them promising candidates for various search challenges including pattern detection in images. Clustered based Neural Networks (CbNN) allow efficient design of AM by providing fast pattern retrieval, especially when implemented in hardware...
Coarse-grained reconfigurable systems are capable of providing flexibility and optimal performance, suitable for nowadays embedded computing systems. The RPCT project has tackled the issue of their complex design, debug and mapping. Demonstration of its potentials and features are presented on an MPEG HEVC motion compensation use case.
Turbo codes are well known error-correcting codes used in many communication standards. However, they suffer from error floors. Recently, a method - denoted as the flip and check algorithm - that lowers the error floor of turbo codes was proposed. This method relies on the identification of the least reliable bits during the turbo decoding process. Gains of about one order of magnitude were reached...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.