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Non-binary low-density parity-check (NB-LDPC) codes over GF(q) (q > 2) have better error-correcting performance than their binary counterparts when the codeword length is moderate. In this paper, a modified trellis-based Min-max decoder is proposed for NB-LDPC codes. By relaxing the constraints on which messages can be included, the trellis syndrome computation is simplified without sacrificing...
A power optimized communication system is proposed in this paper with clock gating technique. The encoder decoder block and the converter circuits are designed using clock gating for power optimization without degrading the system performance. Unwanted switching activities can be much reduced by using clock gating techniques and power saving can be done. Negative latch has been used to generate the...
Electrical stimulation by means of a medical implant is used as a means of restoring the lost functionality of different physiological organs. An active implant which works on a battery or a passive implant which works on power wirelessly transferred to it, could be used for this purpose. The future developments and applications will be in passive implants because of their smaller size and greater...
In an industrial working environment employing multiprocessor communication using UART, noise is likely to affect the data and data may be received with errors. This kind of error occurrence may affect the working of the system resulting in an improper control. Several existing UART designs are incorporating error detection logic. This kind of logic, if detects errors, requires retransmission of corresponding...
The ability to record and replay program execution helps significantly in debugging non-deterministic MPI applications by reproducing message-receive orders. However, the large amount of data that traditional record-and-reply techniques record precludes its practical applicability to massively parallel applications. In this paper, we propose a new compression algorithm, Clock Delta Compression (CDC),...
Intra-chip communication is a major bottleneck in modern multiprocessor system-on-chip (MPSoC) designs. The bus topology is the most common on-chip interconnect technology and bus contention in one of the major issues in bus-based MPSoC designs. Code division multiple access (CDMA) has been proposed as a bus sharing strategy to overcome the bus contention problem. In CDMA, a limited number of orthogonal...
Quasi-cyclic low-density parity-check (QC-LDPC) codes are used in numerous digital communication and storage systems. Layered LDPC decoding converges faster. To further increase the throughput, multiple block rows of the QC parity check matrix can be included in a layer. However, the maximum achievable clock frequency of the prior multi-block-row layered decoder is limited by the long critical path...
Post-silicon validation plays a critical role in exposing design errors in early silicon prototypes. Its effectiveness is conditioned by in-system application of functionally-compliant stimuli for extensive periods of time. This is achieved by expanding on-the-fly randomized functional sequences, which are subjected to user-programmable constraints. In this paper we present a method to extend the...
Reed-Solomon codes are widely used to provide reliable communication, as they are well known for their high data correction rates. However, techniques that best optimize hardware area as well as signal propagation delays are needed in today's applications. In this work, two techniques are investigated and implemented using a hardware description language, synthesized to a XUPV5-LX110t development...
As the portability of electronic systems requires longer battery life, it is necessary that they must have mechanisms in place to reduce the power consumption. One of the techniques used to increase power efficiency at the system level is Dynamic Voltage and Frequency Scaling (DVFS). Variable workload provides an opportunity to scale the voltage and frequency dynamically, so that the power dissipation...
LDPC (Low Density Parity Check) is a channel coding technique is used to correct errors so that the validity of a data transmission on the noise transmission channel guaranteed for accuracy. LDPC is suitable for applications that require a large bandwidth, high reliability, and high noise channel like DVB-S2 (Digital Video Broadcast-Satellite) application. Despite the high level of complexity, LDPC...
This paper demonstrates a clockless stochastic low-density parity-check (LDPC) decoder implemented on a Field-Programmable Gate Array (FPGA). Stochastic computing reduces the wiring complexity necessary for decoding by replacing operations such as multiplication and division with simple logic gates and serial processing. Clockless decoding increases the throughput of the decoder by eliminating the...
The paper presents the details of development of the fiber optic link that will be used to interconnect the various analog signals. Speciality of the link is that the analog signal of frequency up to 1 kHz is transmitted through digital technology. In order to resolve the problem of DC balance and clock/data recovery during the fiber optic data transmission, paper gives a simple and practical solution...
In this paper, a view point of classification of linear codes based on algebraic structure and Local Cyclic Codes is presented. Linear codes are divided into two types (structural and non-structural); almost all these codes are used widely in practice. Local Cyclic Codes are described in relation with other linear codes. These codes are constructed on decompositions of polynomial ring according to...
Frequency-voltage scaling is an efficient technique to tackle the large power consumption of turbo decoders implemented in digital integrated circuits for wireless communications. In this paper, we propose a novel design approach that improves the efficacy of frequency-voltage scaling in turbo decoders. In particular, we present a turbo decoder based on an improved soft-output Viterbi algorithm (SOVA)...
This paper proposes three configuration approaches to improve computing efficiency of a coarse-grained reconfigurable array, including input data relocation, line-based context switching, and loop interval minimization. These proposed approaches fully exploit the parallelism and pipelining of the reconfigurable array, which reduce interval latency when switching the configuration contexts, and therefore...
In this paper we present the architectural design of the tiny scale very long instruction word (VLIW) soft-core processor TinyVLIW8. The processor is designed to achieve a minimal instruction execution time and design size. Although, the instruction repertoire is not large, it is dequate for control tasks, which require decision making that could not easily be implemented in an application specific...
This paper presents a Resolver-to-Digital Converter decoding arithmetic for detecting the velocity and driving distance of automobiles. The application deals with dual synchronous reference frame-based phase-locked loop(DSRF-PLL) to transform the sine and cosine output signals of a resolver into the double SRF(DSRF), from which a decoupling cell(DC) added to attenuate oscillations caused by DSRF....
Extracting data paths in large-scale register-transfer level designs has important usage in automatic verification of synchronous circuits and synthesis of asynchronous circuits. Current tools rely on users to provide the data/control partition or use state-space analyses to extract data paths. Due to the explosion of state-space, the latter method can be used in only small designs. To resolve this...
This paper describes a fully-integrated 77-GHz distant-selective pseudo-random noise coded Doppler radar transceiver in a Silicon-Germanium technology. The transceiver is capable of measuring a vibration or a velocity of a target at a specified distance, which is programmable and can be configured very precisely in the transceiver, and suppressing all other targets elsewhere. It is equipped with two...
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