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This paper presents a configurable 1/2/3 order Butterworth low pass(LP)/complex bandpass (CBP) filter for sub-GHz Applications in a 180-nm CMOS process. The filter employs operational transconductance amplifier (OTA) unit with feedforward capacitor instead of conventional two-stage amplifiers to broaden bandwidth while consuming no extra power. In order to achieve a good noise figure, extra noise...
A fast phase alignment algorithm using successive approximation register (SAR) is proposed for all-digital phase interpolator (PI)-based clock and data recovery circuits (CDR). The SAR algorithm is performed at the beginning of data reception allowing PI-based CDRs to achieve phase lock in few tens of bit-periods. Further phase tracking and data recovery is done by a conventional PI-based CDR to avoid...
Minimizing the total power consumption required for vertical handovers in 4th generation heterogeneous wireless networks is as important as providing users with the best QoS(Quality of Service) continuously. This letter proposes a vertical handover scheme to minimize the total power consumption required for a vertical handover in 4th generation heterogeneous wireless networks, while guaranteeing a...
In this paper, a high gain and wideband input match CMOS low-noise amplifier (LNA) is presented for the ultra-wide band (UWB) application. The main novelty lies in significant improvement in bandwidth by using the inverter cell at the input node, with a peaking inductor at the gate of NMOS device. Self-forward-body-bias (SFBB) concept is also used within the inverter cell to mitigate the trade-off...
In order to reduce inter-core data communication load, increase effective bandwidth, reduce storage space and power consumption, various solutions have been suggested for on-chip networks. The aim of this study is to employ data compression for the packets delivered between cores over the inter-core on-chip network. The packets transferring the cache lines between cores are compressed before transmission...
This paper presents a type-I digital ring-based PLL with wide loop bandwidth to lower the ring oscillator's noise contribution. The in-band noise is addressed using a SAR-ADC-based sampling phase detector (SPD). A stacked reference buffer is also introduced to reduce the transient short-circuit current for low power and low reference spur. The loop delay due to the D flip-flops at filter's output...
This paper presents a reconfigurable SC audio ΣΔ modulator implemented in a 0.18-mm CMOS technology. The 0.4-mm2 ΣΔ modulator, based on a 2-2 MASH architecture, features several different operating modes in which noise-shaping order, number of output bits, sampling rate, and signal bandwidth can be programmed. The power consumption is always minimized for the selected operating mode. The achieved...
A continuous-time ΔΣ ADC with a new high-linearity Gm-cell is presented. A loop filter employing a Gm-C filter is preferable to an active-RC filter with op-amps for low power consumption and a large phase margin. However, distortion caused by the Gm-cell degrades the ADC performance. A cascoded flipped voltage follower Gm-cell is proposed in order to address this problem. Simulation results reveal...
Modern on-chip networks (NoCs) rely on virtual channel (VC) flow control to allow effective utilization of link bandwidth at the cost of more power and longer per-hop latency. Despite many existing optimization techniques for NoCs under VC flow control, we take a further step on questioning its necessity. Our finding is, when the network is not busy, circuit-switching (CS) may already satisfy the...
This paper develops a minimum-power mapping algorithm (MPMA) to minimize power consumption and introduces a random-node mapping algorithm (RNMA) for comparison. Simulation results show that MPMA not only minimize power consumption, but also reduce spectrum resources compared to RNMA.
A low power, 1-V and an area efficient CMOS amperometric potentiostat is designed for gas sensors exploiting the benefits of room temperature ionic liquids. A regulated cascode current mirror is used as current replicating interface, which results in better performance in terms of gain, input/output resistance, bandwidth and linearity. The potentiostat is implemented in 65 nm CMOS standard process,...
We reported a real-time single carrier 400Gb/s system with baud rate of 61GHz. The reality challenges and corresponding DSP solutions are discussed. We show back-to-back as well as propagation performance of the system.
This paper presents a low-power front-end IC for wearable health monitoring systems. The IC, designed in a standard 0.13μm CMOS technology, fully integrates a low-noise analog front-end (AFE) to process the weak bio-signals, followed by an analog-to-digital converter (ADC) to digitize the extracted signals. An AC-coupled driving buffer, that interfaces between the AFE and the ADC is introduced to...
We present TCAD simulation results for the integration of capacitive modulators in a 300mm SOI platform. We show that tuning the capacitor oxide thickness improves the bandwidth and the component efficiency, leading to 860μm active length, 56Gbps data rate and low power consumption (1.2Vpp).
The high power consumption and limited bandwidth of conventional metal interconnects has become the main obstacle to the extension of Moore's Law. Optics is the perfect solution because of its broad bandwidth, low latency, low power consumption, and low crosstalk. The hybrid III–V-on-Si platform has been developed extensively recently as a promising integrated platform to build robust Si-based light...
This paper presents a framework for the systematic design of inductor-less regulated cascode (RGC) stages. Targeting high-speed fiber optic data receiver front-ends, the technique reported combines the symbolic solution of the small-signal model of the RGC and the use of gm/ID based lookup tables to efficiently explore and optimize the resulting design space. A practical design is discussed and implemented...
Cooperative communication can get diversity gain by taking advantage of wireless broadcasting property. But the co-channel interference restricts its performance in multi-hop wireless network. This paper adopts the multi-radio multi-channel technique to fully exploit benefits of cooperative communication. To minimize network power consumption as well as guaranteeing necessary bandwidth for flows,...
Wireless communication networks are expanding with the deployment of small cell networks. Energy efficiency becomes a crucial system design parameter in such systems. One approach to increase the energy efficiency is to allocate radio resources in efficient manner. This is done by developing a QoS based optimization framework for Joint bandwidth and power allocation. Energy efficiency in such systems...
Virtual machine placement (VMP) is the assignment of virtual machines (VMs) to physical hosts (PHs). In this paper, we apply a glowworm swarm optimisation (GSO) algorithm to solve the VMP problem so that the energy consumption, the service level agreement (SLA) violation are minimised. Simulation results show that GSO based VMP algorithm outperforms many of the common VMP algorithms.
The introduction of the Common Public Radio Interface (CPRI) technology allows for a centralization in Base Bandwidth Unit (BBU) of some access functions with advantages in terms of power consumption saving when switching off algorithms are implemented. Unfortunately the advantages of the CPRI technology is to be paid with an increase in bandwidth to be carried between the BBU and the Radio Remote...
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