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Multi-Path TCP (MPTCP) boosts network performance of applications by aggregating bandwidth over multiple paths using sub-flows of the same TCP connection. However, MPTCP suffers from three limitations: (1) it is an end-to-end protocol with no control over the network routes, and sub-flows might end up traversing the same links, (2) it has no dynamic control over choosing the optimal number of sub-flows...
In this paper, we present an architecture and implementation for self-managing cloud application using overlay networks and software defined networking (SDN). Through real world experiments on Amazon EC2 and Smart Applications on Virtual Infrastructure (SAVI) cloud, we demonstrate how our management mechanism autonomously maintains SLAs of application scenarios without provisioning extra resources.
Big data and machine learning applications are posing steadily increasing challenges to the used compute platforms in terms of performance and energy efficiency. In this paper we utilize the highly scalable heterogeneous server platform RECS for evaluation of a wide variety of hardware platforms ranging from general purpose CPUs via ARM-based SoCs to GPGPUs and FPGAs. The self-organizing map, a popular...
Deep Learning (DL) algorithms have become ubiquitous in data analytics. As a result, major computing vendors — including NVIDIA, Intel, AMD and IBM — have architectural road-maps influenced by DL workloads. Furthermore, several vendors have recently advertised new computing products as accelerating DL workloads. Unfortunately, it is difficult for data scientists to quantify the potential of these...
As a potential candidate architecture for 5G systems, cloud radio access network (CRAN) enhances the system's capacity by centralizing the processing and coordination at the central cloud. However, this centralization imposes stringent bandwidth and delay requirements on the fronthaul segment of the network that connects the centralized baseband processing units (BBUs) to the radio units (RUs). Hence,...
Comparison of the dominant emerging memory technologies at the fundamental cell level will be presented. Metrics will be discussed and the technologies will be compared with the objective of judging the suitability for high density memory applications.
Genetic Algorithms (GAs) have been shown to be a very effective optimisation tool on a wide variety of problems. However, they are not without their drawbacks. GAs require time to run, and evolve a bespoke solution to the desired problem in real time. This requirement can prove to be prohibitive in a high-frequency dynamic environment where on-line training time is limited. Neural Networks (NNs) on...
Determining key characteristics of High Performance Computing machines that allow users to predict their performance is an old and recurrent dream. This was, for example, the rationale behind the design of the LogP model that later evolved into many variants (LogGP, LogGPS, LoGPS, ) to cope with the evolution and complexity of network technology. Although the network has received a lot of attention,...
HBM (High Bandwidth Memory) is an emerging standard DRAM solution that can achieve breakthrough bandwidth of higher than 256GBps while reducing the power consumption as well. It has stacked DRAM architecture with core DRAM dies on top of a base logic die, based on the TSV and die stacking technologies. In this paper, the HBM architecture is introduced and a comparison of its generations is provided...
The outstanding advances in computing as well as the explosion of devices and services requirements are making communication mobile networking more and more complex to manage. In addition, multimedia services such as provided by the IP Multimedia Subsystem (IMS) require a dynamic Quality of Service (QoS) management. However, traditional Long Term Evolution (LTE) networking approaches have become too...
Today's supercomputers are moving towards deployment of many-core processors like Intel Xeon Phi Knights Landing (KNL), to deliver high compute and memory capacity. Applications executing on such many-core platforms with improved vectorization require high memory bandwidth. To improve performance, architectures like Knights Landing include a high bandwidth and low capacity in-package high bandwidth...
GPUs are often limited by off-chip memory bandwidth. With the advent of general-purpose computing on GPUs, a cache hierarchy has been introduced to filter the bandwidth demand to the off-chip memory. However, the cache hierarchy presents its own bandwidth limitations in sustaining such high levels of memory traffic. In this paper, we characterize the bandwidth bottlenecks present across the memory...
This work explores the design space (bandwidthand port configuration) for an FPGA-based top-of-rack switchand, use our implementation, to provide an insight on which ofthese options is the best. We also propose an architecture fora rack-scale computer built on a printed circuit board (PCB) exploiting the FPGA-based switch.
A 0.5–3GHz true-time delay (TTD) phase shifter circuit is implemented. Basing on active delay cells and active switches, the coarse delay is achieved. The LC artificial transmission line (ATL) provides continuous delay. The delay variation of the total delay is less than 2.4%. Using broadband matching and shunt peaking techniques, larger bandwidth and flatter group delay is obtained in phase shifter...
This paper presents two wideband GaAs MMIC driver power amplifiers (PAs) suitable for X and Ku bands. The required number of stages and number of branches in each stage for an M-stage driver PA architecture is analyzed. Design of wideband matching networks for monolithic microwave integrated circuit (MMIC) driver PAs is explained and design parameters of a cascaded K-section T matching network (MN)...
In video decoder applications, motion compensation (MC) is bandwidth consuming because of the non-regular memory access. Especially with the popularity of UHD video and the development of new coding standard (HEVC), external memory bandwidth becomes a crucial bottleneck. In this paper, we propose an area efficiency cache-based bandwidth optimization strategy to minimize the memory bandwidth. First...
The size of data chunk diverges from 101 to 1010 bits. Generally, if a network carries in a way both of big size data and small size data, the performance is extremely degraded by the big size data. Then, we propose to select a wireless cell among of multiple cells by referring context information such as data size and user's situation such as moving velocity. Especially, we show the improvement on...
We propose an architecture that incorporates a robust and agile primary user (PU) detection, accompanied by a dynamic OFDM spectrum allocation scheme. By exploiting the capabilities of a 2×2 MIMO PCIe SDR device we are able to maximize the usage of the available spectrum with the minimal PU disturbance.
Infrastructure monitoring applications currently lack a cost-effective and reliable solution for supporting the last communication hop for low-power devices. The use of cellular infrastructure requires contracts and complex radios that are often too power hungry and cost prohibitive for sensing applications that require just a few bits of data each day. New low-power, sub-GHz, long-range radios are...
A reflectarray antenna composed of double cross loop elements of varying arm length printed on a conductor-backed substrate is introduced. Two different realizations are presented: in the first design, the lengths of both constituent arms of the cell elements are varied whereas the length of only one of the two arms is varied in the second design. Prototype reflectarrays were fabricated and measured...
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