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Assertion Based Verification (ABV) is one of the widely used verification technique to enhance the verification quality and reduce the debugging time of complex system-on-chip (SOC) designs in order to speedup the verification process. A verification environment to verify an AMBA-AHB (Advanced High Performance Bus) by using SystemVerilog Assertion (SVA) is presented in this paper as it can easily...
The paper discusses step-by-step practical flow involved in applying dynamic bandwidth management (DBM) to large industrial system-on-chip (SoC) designs deploying embedded test data compression.
A 10–20 Gb/s clock and data recovery (CDR) circuit with frequency tracking is presented. Two digital phase interpolators (PIs) are used to track the frequency of input data. The loop bandwidth of the CDR circuit is adaptively adjusted. A mixed-mode PI is used to generate the recovered clock. This CDR circuit is fabricated in a 40nm CMOS process and its area is 0.33×1.0 mm2. Its power consumption is...
This paper investigates low-phase-noise and low-spur subharmonically injection-locked phase-locked loop (IL-PLL) circuits. Here the multiple injection is applied for the effective injection locking. In order to reduce the spur, a high-pass filter is inserted into the signal path of the injection for decreasing the subharmonic elements of injections. The testchip is designed and fabricated in the 0...
This paper introduces a fully-integrated wireline transmitter operating at 28Gb/s. The transmitter incorporates a 3-tap Feed-Forward-Equalizer (FFE) with Flipflop-based delay to equalize the channel. T-coil networks are used with ESD protection circuits at transmitter's output to realize impedance matching and bandwidth enhancement. The transmitter is fabricated in 65nm CMOS technology. The measurement...
A wide-locking range divide-by-4 static frequency divider for the mm-wave wireless applications is proposed. The capacitive-bridged inductive shunt peaking technique is investigated for widening the locking range and a compact layout area. The divider is realized in 65nm LP CMOS with a small area of 100μm × 160μm occupied. Measurement results show the present divider achieves an operation range percentage...
A Traveling-Wave ADC based on spatially interleaved sampling on a synthetic transmission line is proposed. Signal propagation on the transmission line generates the interleaving delay. This architecture enables extremely small sampling periods which allow for high sampling frequencies. Furthermore, the loaded T-line provides a broadband input impedance to enable extended input frequencies. The design...
This paper presents a continuous time sigma delta ADC for 50 MHz bandwidth with 80 dB resolution, which overcomes the shortcomings of known architectures. It incorporates a 5 bit flash ADC as a quantizer with a current steering feedback DAC employing dynamic element matching. The main feedback path and the fast feedback path around the quantizer have shifted delays to compensate for the excess loop...
Wireless localization systems are of great importance for a variety of modern applications. Recently, cooperation among agents (nodes with unknown positions) becomes attractive in localization networks, especially in the infrastructure-limited scenario. In many cases, synchronization of the agents' clocks to the anchors (nodes with known positions) has to be performed together with the localization...
This paper introduces an ultra-low voltage open loop VCO-based ADC with background calibration for ultra-low power applications. A novel calibration scheme is proposed to calibrate the nonlinear voltage-to-frequency tuning curve of the VCO. A replica VCO is used to compute the correction coefficients and the corrected values are stored in a lookup table. The proposed calibration method is at least...
This paper presents a novel pipeline configuration for wireless applications. Redundancy and multi sampling of the input techniques are used for overcoming the main limitations of pipeline ADCs. A special pre-amplifier with built-in thresholds generation is also discussed. The circuit, designed and simulated in a 65-nm CMOS technology, achieves 2.66 GS/s and 8-bit resolution. The supply voltage is...
A 800-Mb/s optical receiver based on pulse-position-modulation (PPM) scheme is presented. The proposed PPM receiver can recover the clock without any help of a reference clock or a forwarded clock. As a result, the number of wire and pin count is minimized. Moreover, the proposed receiver employs optical front-en d circuits for fiber-optic communications which is optimized for low-power operation...
This study investigates the design issues of a phase-locked loop (PLL)-based point-to-point (P2P) high-speed interface with periodically embedded clock encoding (PECE). Interfaces of this type are the mainstream serial links for 4K2K or higher resolution applications in the display industry. Early works mainly focus on delay-locked loop (DLL)-based or Hogge-type CDR implementation, while this work...
Issues of High Performance Computer (HPC) system diagnosis, automated system management, and resource-aware computing, are all dependent on high fidelity, system wide, persistent monitoring. Development and deployment of an effective persistent system wide monitoring service at large-scale presents a number of challenges, particularly when collecting data at the granularities needed to resolve features...
A variable-rate digital signal processor capable of processing samples with a variable sampling rate is discussed in this paper. The clock rate in the DSP tracks the input sampling rate. Compared to a fixed-rate DSP, the proposed one has a lower output data rate and thus consumes less power for computation. A reconstruction filter with a variable cutoff frequency is used to reconstruct the output...
An explosive growth in the number of IT devices connected to a central system requires massive growth in aggregate bandwidth of wireline communications. As a result, a multi channel architecture is necessary in the high-speed I/O link to meet the ever increasing bandwidth requirement. Forwarded clock (FC) architecture offers the most efficient solution for the multi-channel I/O owing to the shared...
This paper presents a 96.6-dB-peak-SNDR and 50-kHz-bandwidth switched-capacitor delta-sigma modulator for ADC operating at 1.8 V and consuming 7.9 mW. This performance is achieved by the introduction of Class-AB single-stage switched variable-mirror amplifiers (VMAs) combined with an optimized architecture and a 5-phase switched-capacitor scheme. The resulting 1.8-mm2 delta-sigma modulator is integrated...
An increase in electromagnetic interference (EMI) noise in mobile application directly affects the performance of the other chips or antenna that can lead to the degradation of total isotropic sensitivity (TIS) and system reliability. According to our near fiend scanning (NFS) results, electromagnetic (EM) noise emitted from AP-LPDDR memory interface in a package on package (POP) structure was found...
This paper describes the implementation of a continuous-time Delta-Sigma modulator for wireless, instrumentation and measurement applications. The Delta-Sigma modulator employs Gm-C based integrator to form a 4th-order noise-shaping loop. The modulator can achieve 70.7dB of SNDR in 2MHz bandwidth with an oversampling ratio of 40 and single-bit quantization. The modulator is designed in TSMC 0.25μm...
This paper presents an analysis and system-level design of an incremental sigma-delta converter (IΣΔ ADC) in order to explore a possible solution to low power multi-channel applications. The problem of using classic ΣΔ ADCs for applications which require time multiplexed signals will be discussed. The IΣΔ ADCs are characterized for resetting all memory elements present in ΣΔ modulator core and digital...
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