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A voltage domain correction technique is proposed to mitigate the timing skew errors in time interleaved (TI) analog to digital converters (ADCs). The proposed technique exploits the fact that any timing skew in the sampling edge of a clock results in a corresponding error in sampled voltage that propagates through the ADC. The technique intends to cancel this voltage error by applying a correction...
Incremental analog to digital converters (lADCs) are aimed at converting low frequency signals with high accuracy. However the use of high oversampling ratios (OSR) usually decreases the conversion speed making them energy inefficient. The first integrator also consumes a lot of power due to high settling requirements, if a single bit quantizer is used. This paper introduces a two step feedforward...
We propose a track-and-hold-less flash-like stroboscopic ADC for use in the implementation of an undersampling ultra-wide-band radar receiver. The ADC is comprised of a number of sub-ADCs in which each sub-ADC is a multi-pass ADC. Strong-Arm latch with tens of GHz of sampling bandwidth is utilized as the core of each multi-pass ADC. The prototype of the ADC achieves a THD of ∼23dB with a THD ERBW...
This paper presents a millimeter-wave (mmWave) wideband sliding correlator channel sounder with flexibility to operate at various transmission rates. The channel sounder can transmit and receive up to 1 GHz of RF null-to-null bandwidth while measuring a 2 nanosecond multipath time resolution. The system architecture takes advantage of field-programmable gate arrays (FPGAs), high-speed digital-to-analog...
Correctly maintained synchronization between devices is very important in deterministic networks like TTEthernet where is used AS6802 standard for this purposes. In this paper is depicted how to calculate number of integration cycles per cluster period depending on accuracy of clocks implemented in network devices. Influence of the number of integration cycles to bandwidth utilization is analyzed...
In this paper a simple method of design and implementation of a LFM (linear frequency modulation) waveform or chirp of 3μsec pulse duration with 200MHz bandwidth, using DDS (direct digital synthesis) and FPGA [Virtex4 LX25FF668 (−10)] is explained. The design and implementation of LFM consists of, 1) Design and realization of spot frequency generation using DDS [AD9858]. 2) Design and realization...
In view of the numerous clock domain crossings found in modern systems-on-chip and multicore architectures precise metastability characterization is a fundamental task. We propose a conceptually novel approach for the experimental assessment of upset rate over resolution time that is usually employed to extract the relevant characteristics. Our method is based on connecting a time-to-digital converter...
One of the prevalent methods to achieve clock synchronization in star topology based wireless network, is by periodic transmission of a "Beacon" message from the controller. Using this message other nodes locate the start of the time frame established by the controller. This technique has not been energy efficient in case of low duty cycle applications, where the nodes have to receive the...
Communications systems make heavy use of FPGAs; their programmability allows system designers to keep up with emerging protocols and their high-speed transceivers enable high bandwidth designs. While FPGAs are extensively used for packet parsing, inspection and classification, they have seen less use as the switch fabric between network ports. However, recent work has proposed embedding a network-on-chip...
A point-to-point interface with a clock embedded scheme (CES) in Fig. 29.5.1 is generally adopted in an intra-panel interface due to the poor signal integrity of the multi-drop topology, data and clock channel skews and EMI emission from the forwarded clock signal channels. Clock recovery in RX without a reference clock channel is usually carried out using one of two type of data encoding schemes,...
Software defined radios and wideband instrumentation demand the ability to digitize wide BW RF signals with moderately high dynamic range. A 12b 10GS/s ADC with an input analog bandwidth of 7.4GHz is developed for such applications in 28nm CMOS. The ADC achieves an SNR of 56dB, SNDR of 55dB and SFDR of 64dB with a 4GHz input at 10GS/s, and realizes an NSD of −157dBFS/Hz (i.e. DR = 60dB) while dissipating...
Cognitive computing and cloud infrastructure require flexible, connectable, and scalable processors with extreme IO bandwidth. With 4 distinct chip configurations, the POWER9 family of chips delivers multiple options for memory ports, core thread counts, and accelerator options to address this need. The 24-core scale-out processor is implemented in 14nm SOI FinFET technology [1] and contains 8.0B...
As we move to higher data rates, the performance of clock and data recovery (CDR) circuits becomes increasingly important in maintaining low bit error rates (BER) in wireline links. Digital CDRs are popular in part for their robustness, but their use of bang-bang phase detectors (BB-PD) makes their performance sensitive to changes in jitter caused by PVT variations, crosstalk or power supply noise...
The applications of speech interfaces, commonly used for search and personal assistants, are diversifying to include wearables, appliances, and robots. Hardware-accelerated automatic speech recognition (ASR) is needed for scenarios that are constrained by power, system complexity, or latency. Furthermore, a wakeup mechanism, such as voice activity detection (VAD), is needed to power gate the ASR and...
Over the last years, GDDR5 has emerged as the dominant standard for applications requiring high system bandwidth like graphic cards and game consoles. However, GDDR5 data rates are saturating due to limitations in the clock frequency and column-access cycle time (tCCD). To reach the data rate of 9Gb/s/pin [1], a GDDR5 DRAM has to be clocked at 2.25GHz and operate at a tCCD of 888ps. This combination...
Electrical link migration requires serial interfaces to operate at increasing data rates. Despite the fact that most standards still employ NRZ, practical signal integrity constraints demand PAM-4 modulation, especially for some interconnect applications and low-loss profiles [1]. Nevertheless, compared to NRZ, the design of high-speed PAM-4 transmitters entails several challenges. Achieving high...
Ultra-narrow-band (UNB) signaling is an enabling technology for low-power wide-area (LPWA) networks for the “Internet-of-Things”. Indeed, UNB signaling, based on spectrally efficient modulations such as DBPSK, simultaneously optimizes network capacity while maximizing the communication link budget. However, UNB signaling poses many technical challenges. In the receiver, carrier frequency offsets (CFO)...
Optical on-chip communication is considered a promising candidate to overcome latency and energy bottlenecks of electrical interconnects. Although recently proposed hybrid Networks-on-chip (NoCs), which implement both electrical and optical links, improve power efficiency, they often fail to combine these two interconnect technologies efficiently and suffer from considerable laser power overheads...
This paper presents the design procedure for a 2nd_order two-path Discrete-Time Time-Interleaved (DTTI) ΔΣ modulator from a conventional single-loop 2nd-order Discrete-Time (DT) ΔΣ modulator through the use of time domain equations and time-interleaving concepts [1]. The resulting modulator is free from the delayless feedback path and has only one set of integrators. The delayless feedback path issue...
The memory wall problem is due to the imbalanced developments and separation of processors and memories. It is becoming acute as more and more processor cores are integrated into a single chip and demand higher memory bandwidth through limited chip pins. Optical memory interconnection network (OMIN) promises high bandwidth, bandwidth density, and energy efficiency, and can potentially alleviate the...
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