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In the last decade, OpenCL has sparked the interest of the computing world as it is a language based on an open standard that can run on many different heterogeneous platforms. This standard is continuously evolving to adapt to various use cases of different platforms. For example, with requests from the FPGA community, the pipe construct was added to the standard to facilitate the implementation...
A software/hardware co-design system for a Trax solver is proposed. Implementation of Trax AI is challenging due to its complicated rules, so we adopted an embedded system called Zynq (Zynq-7000 AP SoC) and introduced a High Level Synthesis (HLS) design. We also added Deep Q-Network, a machine learning algorithm, to the system for use as an evaluation function. Our solver automatically optimizes its...
With the fundamental trade-off between speed and sensitivity, existing quantitative phase imaging (QPI) systems for diagnostics and cell classification are often limited to batch processing only small amount of offline data. While quantitative asymmetric-detection time-stretch optical microscopy (Q-ATOM) offers a unique optical platform for ultrafast and high-sensitivity quantitative phase cellular...
Modern industrial process instrumentation systems like radar based flow meters demand for scalable modular hardware platforms to meet the requirements for integration in heterogeneous Cyber-Physical Systems (CPS). Recent advances in System on Chip (SoC) technology allow integration of multichannel frequency modulated continuous wave (FMCW) radar sensors with real-time signal processing capabilities...
There is now significant interest in OpenCL for FPGAs because it is the first time the FPGA vendors have provided a programming model and a computing platform with integrated high-level synthesis. OpenCL is intended for heterogenous platforms, not just FPGAs, and the standard continues to evolve. Recently, OpenCL has introduced Shared Virtual Memory (SVM) with the goal of simplifying the programming...
In recent years, high-level languages and compilers, such as OpenCL have improved both productivity and FPGA adoption on a wider scale. One of the challenges in the design of high-performance stream FPGA applications is iterative manual optimization of the numerous application buffers (e.g., arrays, FIFOs and scratch-pads). First, to achieve the desired throughput, the programmer faces the burden...
Increasing computation demands with limited power budget require more energy-efficient designs without performance degradation in embedded systems and mobile computing platforms. Reconfigurable computing is an alternative to optimize both performance and power consumption. However, due to the complexity of hardware design, implementing dedicated accelerators usually lacks flexibility and productivity...
Design advancements in semiconductor industry have resulted in shrinking schedules of time-to-market and improved quality assurance of the chips to be in perfect tandem with their specifications. Hence, Post-Silicon Validation, having a significant percentage in time-to-money, becomes one of the most highly leveraged steps in chip implementation. This also puts more pressure to reduce the validation...
A sensor platform is a station equipped with extensive sensor and communication systems, which provide space based detection and alert capabilities. It consists of low-power, embedded computing devices known as motes, which use sensors to collect measurements from the physical world and its inhabitants. In this paper, an ARM-based sensor platform running a Linux Operating System is designed and implemented...
Coarse-Grained Reconfigurable Architecture (CGRA) is a promising accelerator when considering both high performance and high power-efficiency. One of the challenges that CGRAs are confronting is to accelerate loops with control flow (if-then-else structures). Existing techniques employ predication to accelerate the conditionals but cannot accelerate nested conditionals efficiently. The state-of-the-art...
Recently, the OpenCL hardware-software co-design methodology has gained traction in realizing effective parallel architecture designs in heterogeneous FPGA platforms. In fact, the portability of OpenCL on hardware ready platforms such as GPU or multicore CPU enables ease of design verification. This is true especially for parallel algorithms before implementing them using cumbersome HDL-based RTL...
A recent trend for big data analytics is to provide heterogeneous architectures to allow support for hardware specialization. Considering the time dedicated to create such hardware implementations, an analysis that estimates how much benefit we gain in terms of speed and energy efficiency, through offloading various functions to hardware would be necessary. This work analyzes data mining and machine...
We present an ASIC architecture with coarse-grain reconfigurability that uses accelerators to improve performance over fine-grain reconfigurable architectures. A reconfigurable FFT ASIC was built as a proof of concept, and it successfully demonstrated valid switch operation for reconfiguration.
FPGA-based reconfigurable computing is finding its way into a wide range of application areas in which high performance and low power consumption are paramount. However, FPGA-application development using hardware-description languages (HDLs) faces many productivity challenges that limit its wide adoption, including a steep learning curve and lengthy compilation. High-level synthesis (HLS) languages...
Combining several types of devices and architectures is at the heart of heterogeneous computing's power efficiency advantage, but the strength of heterogeneous systems is also their Achilles heel, i.e. the diversity of the devices and ecosystems needed to maintain them present major technological challenges. Some of the biggest challenges are in the realm of system programing. We believe that for...
In order to improve the real-time performance and reliability of the drive system for infrared image array, this paper designs an embedded drive system. With MPC8315 as the processing core, this system takes reflective memory network as the transmission unit. In order to verify and analyze the performance of the embedded drive system for the infrared image array, this paper sets up a test platform...
Data centers require many low-level network services to implement high-level applications. Key-Value Store (KVS) is a critical service that associates values with keys and allows machines to share these associations over a network. Mostexisting KVS systems run in software and scale out by running parallel processes on multiple microprocessor cores to increase throughput. In this paper, we take an...
Compute-intensive applications incorporate ever increasing data processing requirements on hardware systems. Many of these applications have only recently become feasible thanks to the increasing computing power of modern processors. The Matlab language is uniquely situated to support the description of these compute-intensive scientific applications, and consequently has been continuously improved...
In this paper, we propose an FPGA memory hierarchy based on the OpenCL memory model. The memory hierarchy allows application-specific memory optimizations during design compilation using information provided in OpenCL kernels. With the proposed memory hierarchy, FPGA application developers can focus on their designs in OpenCL kernel codes, and their designs can be synthesized into FPGA hardware via...
The CHIME Pathfinder is a new interferometric radio telescope that uses a hybrid FPGA/GPU FX correlator. The GPU-based X-engine of this correlator processes over 819 Gb/s of 4+4-bit complex astronomical data from N=256 inputs across a 400MHz radio band. A software framework is presented to manage this real-time data flow, which allows each of 16 processing servers to handle 51.2 Gb/s of astronomical...
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