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A wideband CMOS mm-Wave amplitude detector for on-chip self-test and calibration is presented. The high-conversion-gain detector enables accurate on-chip amplitude measurements and allows for the prediction of key RF parameters. The detector operates across the 60 GHz band and achieves a dynamic range of 0-0.5 V and a sensitivity of -9 V/V. The detector's practical use in mm-wave Built-in-Self-Test...
The design of Class E Amplifiers is more difficult than other type of amplifiers as it is imposed by time domain constraints. This paper presents the performance analysis of Mode Locked class E Power Amplifiers using State Space Analysis Algorithm. A technique is introduced which is used to curb the negative effect of parasitic resistance of DC Feed Choke and the Power Amplifier operates at 2.4GHz...
A distributed low-noise amplifier (LNA) employing novel transmission lines and inductors was designed in a standard 0.18-μm CMOS process. The new LNA provides significant improvement in performance and size with less than 13 dB return loss from DC to 17 GHz, average gain of 8 ± 0.2 dB from DC to 20 GHz, noise figure of 3.4-5 dB from 0.5-19 GHz, power consumption of 34.2 mW, and 1.05 × 0.37 mm2 chip...
A single-chip broadband CMOS receiver front-end, integrating a low-noise amplifier (LNA), a correlator and a template pulse generator, was investigated in non-sinusoidal time-domain environment for possible use as a carrierless ultra-wideband (UWB) receiver front-end. Particularly, the CMOS LNA and the multiplier making up the core component of the correlator were designed, fabricated and tested to...
Chopping technique is an efficient approach to decrease the low-frequency offset and 1/f noise of amplifiers. In this paper, a low-power low-noise CMOS chopper amplifier is designed. This chopper amplifier is composed of a two-stage amplifier. The high output impedance of the first stage and the equivalent Miller capacitance of the second stage amplifier constitute together a low pass filter to filter...
In this paper, a new method for analog design reuse during technology migration is proposed. Previous works ignore the variance of technology parameters. Accordingly, bases on gm/id methodology and ACM model, our methodology adopts an extra pre-extraction step for parameters deciding. This enables a practical description of MOS transistor working state and is therefore more precisely in deciding the...
An on-chip transformer-based digital isolator for intelligent power management (IPM) systems is proposed. It greatly reduces the number of chips in IPM systems by allowing integration of isolators in a CMOS chip together with MPUs or gate drivers. With a proposed pulse generation / detection scheme that enables a 5V standard CMOS transistor to utilize GHz-band signals, transformer area is reduced...
An ultra-wideband (UWB) 3.1- to 10.6-GHz low noise amplifier (LNA) employing a common-gate stage for wideband input matching and tunability with neural network is presented In this paper. Designed in a commercial 0.18-μm 1.8-V standard RFCMOS technology, the proposed UWB LNA achieves fully on-chip circuit implementation, contributing to the realization of a single-chip CMOS UWB receiver. The proposed...
A CMOS bandgap reference (BGR) capable of operating at supply voltage of 0.9V was proposed in this paper. To guarantee its normal operation at ultra low supply voltage, the substrate bias techniques is used to reduce the threshold voltage. Meanwhile, an amplifier biased by subthreshold current is designed. This circuit is designed in tsmc 0.35μm CMOS technology. An average reference voltage of 658mV...
This paper presents a novel VGA (Variable Gain Amplifier) with an embedded analog FIR (Finite Impulse Response) filter architecture. The idea is based on a modified version of the integrate and dump circuit. The proposed modifications allow altering the frequency response of the circuit without significantly increasing the circuit complexity along with maintaining acceptable gain control range, noise...
This paper discusses noise figure optimization techniques for a noise-cancelling single-ended-to-differential CMOS low-noise amplifier (LNA). In [1], a low noise figure was obtained through cancellation of the drain noise of the common-gate transistor. Contour plots demonstrate that drain noise cancellation does not guarantee an optimal noise figure. The optimal noise figure is achieved by minimizing...
In this paper, a low-power broadband automatic-gain-control (AGC) amplifier targeted for use in the Square Kilometer Array (SKA) is presented. The AGC is composed of an input power-match circuit, a linear-in-dB output variable gain amplifier (VGA), a power detector (PD), an error amplifier, a comparator and a loop filter. The input stage is power matched to 100 Ω differential source impedance, achieves...
This paper presents a double-balanced CMOS down-conversion mixer for 60-GHz receivers, although the mixer is designed specifically for a phased array receiver architecture. The proposed mixer uses two on-chip baluns implemented with the two top metal layers in a 0.13-μm CMOS technology. The baluns provide 180° differential outputs from applied single-ended input at the radio-frequency (RF) and local-oscillator...
In this paper a 0.9V high gain, high speed two-stage Op-Amp is designed and simulated in a 0.18μm CMOS technology. Using both bulk-driven and positive feedback techniques, the dc gain of this Op-Amp is increased about 18.5dB without consuming more power. In addition, the frequency response of the proposed Op-Amp is investigated. Compared to the conventional Op-Amp structure, it is shown that in the...
CMOS vision sensors, as all electronic systems, are very sensitive to temperature variation. Mainly, this sensitivity limits their DC electrical behaviour. So far, no elegant integrated solution of this shortcoming has been proposed. In this paper, we introduce a compensation technique within the circuit in order to decrease power consumption and response time. To overcome this defect caused by temperature,...
A microwave operational transconductance amplifier (OTA) using a feedforward-regulated cascode stage and an active inductor load is proposed in this paper. The use of the feedforward regulation mechanism provides the OTA with a very wide bandwidth of over 10 GHz while the active inductor load contributes to the OTA's high linearity performance. Furthermore, the transconductance of the OTA can be varied...
In this paper, the use of body biasing to control gain, linearity, and noise figure in CMOS low-noise amplifiers (LNAs) is investigated. As a proof of concept, a 60-GHz 4-stage cascode CMOS variable-gain LNA is designed and laid out in a 6 5nm CMOS technology. To improve the accuracy of the post-layout simulations, all inductors are modeled and simulated with a 3-dimentional electromagnetic solver...
A compact high-accuracy rail-to-rail CMOS operational amplifier (Op-Amp) is presented using strong inversion techniques to achieve power consumption of 90μW under 1.8V supply voltage. Two complementary differential pair techniques and one-versus-three current mirror compensation techniques are adopted to realize wide input dynamic range, while the output stage provides rail-to-rail output drive through...
Providing ESD protection for wideband RF CMOS LNAs is a challenging task: it requires both ESD and RF design skills in order to achieve high ESD robustness, while maintaining the overall RF performance. In this paper, an overview of the different wideband RF ESD protection strategies used in the literature is presented.
This paper demonstrates the design of a radio frequency (RF) class A power amplifiers for WiMAX application using TSMC 0.18μm CMOS technology. A novel two-stage cascode common-source amplifier and a load-pull output matched power amplifier are designed for the WiMAX application of 2.5 GHz transmitting frequency. The designed power amplifier exhibits 19.8 dBm of 1-dB compression point, 24.1 dBm of...
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