The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
The development of Wireless Body Area Network (WBAN) is a key point enabling the mobility health. Among the most critical constrains in WBAN implementation is the power consumption of wireless featuring nodes. This work focuses on the development of ultra low power radio building blocks dedicated to 2.4 GHz ISM band. A novel design approach based on device optimization is first presented. It is then...
This paper reports comparisons between RTW VCO and LC QVCO 12 GHz PLLs, designed in a 130 nm CMOS technology. The phase noise at 1MHz offset from the carrier is −102 dBc/Hz for the RTW VCO PLL and −98 dBc/Hz for the LC QVCO PLL, and the power consumption is 39mW and 17 mW, respectively.
Cognitive Radios are expected to provide in the near future an alternative solution for the heavy usage of the spectrum, especially for commercial purposes. Wideband front-end circuits, as low-noise amplifiers (LNAs), are then an alternative. This paper presents a new CMOS topology capable of simultaneous noise canceling and broadband input power matching for the range of 50MHz to 5GHz with flat power...
A new distributed amplifier (DA) topology is proposed. This topology is the combination of the conventional distributed amplifier (CDA) and the cascaded single-stage distributed amplifier (CSSDA), which makes wideband amplifier by considering the gain, noise figure and output power simultaneously. From the measurements, the DA has a small signal gain of 20.5 dB, a 3-dB bandwidth of 35 GHz, and a gain-bandwidth...
This paper presents a K-band low noise amplifier (LNA) co-designed with ESD protection circuit in 40-nm CMOS technology. By treating ESD devices as a part of the input matching network, an ESD protected 24-GHz LNA is demonstrated with a NF of 3.2 dB under a power consumption of only 4.1 mW. The ESD protection network is composed of dual-diode and a gate-driven power clamp achieving an ESD level of...
This paper briefly analyses the noise, bandwidth and linearity performance advantage of nanometer CMOS current-mode circuits compared to their voltage-mode counterparts and proposes a new current-mode receiver front-end targeting low-power wideband wireless applications. The proposed 65nm CMOS current-mode receiver front-end comprises a current-mode LNA, and passive mixers, and covers all WiMAX/LTE...
A highly linear active mixer is introduced for IEEE 802.11 applications. It uses a new technique to remove the common mode currents in all frequencies. In zero-IF receivers, IIP2 is the most important parameter which shows the output's IM2 nonlinearity. In this paper, IIP2 improves more than 17 dBm by removing its common mode current. Also, the new technique, improves IIP3 more than 5dBm in comparison...
We present a wide dynamic range, dual-mode low noise amplifier (LNA) operating in 0.8 to 6 GHz, which is suitable for a multi-band multi-standard front-end in a scaled CMOS technology and a low supply voltage operation. The digitally controlled high-sensitivity and high-linearity modes enable a low noise and a high linearity according to an input power to the LNA. In measurement, the LNA shows a power...
This paper analyses the use of continuously-tuned Low Noise Amplifiers (LNAs) for the implementation of the next generation of software-defined radio receivers. Two LNA circuits are discussed. One is based on a folded cascode stage and the other one consists on a two-stage inductively degenerated common-source configuration. Both LNAs - designed and implemented in a 1-V 90-nm CMOS technology - employ...
Modern wireless systems are increasingly incorporating adaptability to operate at low power under varying channel conditions and to increase yield under severe process variation. Effective adaptation requires built in tuning knobs in the RF front end circuits. Due to the sensitive nature of RF circuits traditional turning knobs affect more than one specification simultaneously. To ensure optimal adaptation...
CMOS imagers that consist of a pixel array of image sensors, an analog-to-digital converter (ADC) array, and image signal processors (ISPs) have been widely adopted in various imaging applications. Since the array of ADCs in the imager jointly and concurrently converts the pixel data for producing a final image, their test specifications and calibration targets should consider both intra-ADC linearity...
We have used silicon technologies to build highly dense phased array for X to W-band applications. Typical designs include an 8-element 8-16 GHz SiGe phased array receiver, a 16-element 30-50 GHz SiGe transmit phased array, a miniature (<; 3mm2) and low power (<;100 mW) CMOS phased array receiver at 24 GHz, and a 4-element SiGe/CMOS Tx/Rx phased array at 34-38 GHz with 5-bit amplitude and phase...
A 0.18 μm CMOS RF receiver front-end applying in DSRC systems is presented in this paper. The proposed receiver front-end includes the current-reused LNA, the folded Giber cell mixer, and the Colpitts VCO. Also, this paper presents the design methodology and application of the transformer balun for RFIC. The measured results of the proposed receiver front-end show the input return loss of 30.5 dB,...
A low-power (2.76 mW) common-gate (CG) low-noise amplifier (LNA) for ultra-wideband (UWB) systems using standard 0.18 μm CMOS technology is demonstrated. Instead of the traditional single parallel inductor (LS1 only), we propose a new matching network consisting of a series LS1-RS1 in series with a parallel LS2-RS2 to enhance the input matching bandwidth. Flat and high S21 was achieved by using the...
This paper presents an highly-linear ultrawideband balun low-noise amplifier (LNA) for cognitive radios covering the 50MHz to 10GHz band. It exploits a three-stage dc-coupled common-source amplifier, with RC degeneration at the last stage to optimize the gain, linearity and output gain-phase balancing. Designed in 65nm CMOS, throughout the covered band the simulated voltage gain is ∼24dB whereas the...
An ultra-wideband (UWB), high gain and low-noise amplifier (LNA) for wireless applications is presented in this paper. Operating at the frequency band of 0.8-6.0 GHz and fabricated in TSMC 0.18-um technology, the measured results show the gain of 17-19 dB, the noise figure (NF) less than 4.8 dB, the input third-order intercept point (IIP3) of -17 dBm, the reverse isolation less than -25 dB and the...
This paper a noise-canceling low-noise Amplifier (LNA) intended for WiMAX applications has been designed using 0.18 micrometer CMOS technology. Wide-band input and output impedance matching, low Noise-Figure (NF), reasonable voltage gain and low power consumption are the main challenges of Low Noise Amplifier design. In this design frequency band as well as a lower chip area and noise cancellation...
In this paper, a Q-band common source low noise amplifier (LNA) using 90-nm standard RF-CMOS technology is proposed. The design methodologies for millimeter-wave (MMW) amplifiers are discussed. The post layout simulation results show that S11 is lower than -14 dB and S22 is -11 dB at the peak gain of 14.6 dB at 37.5 GHz with 9.4 GHz bandwidth, the minimum noise figure is lower than 5.5 dB, the input...
With a cut-off frequency in excess of 250GHz, nanometer-scale CMOS technology is rapidly expanding from Radio Frequency to mm-Waves applications. Frequency dividers are key building blocks for LO generation in wireless transceivers and clock synchronization in front-ends for wire-line and optical communications. Dividers based on traditional static CML latches work over a wide band but power dissipation...
In this paper, a 2.5GHz fully differential tuned LNA with integrated T/R switch is designed in a High-K metal gate 32nm digital CMOS process, and packaged in an SoC-compatible flip-chip package. Reliability constraints of the package severely limit the ability to depopulate soldering bumps, and RF components must be designed taking the bump location into account. The LNA achieves a 3.5dB NF, -5dBm...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.