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Digital designs makes use of Flip-flops (FFs) as the basic storage element. Pulse-triggered FF (P-FF), which is more popular than the master-slave based FF in high-speed applications consists of a single latch structure, hence Explicit type pulse trigger generator with pulse width control with performance optimization in power, delay, and area, design space exploration is important, In Explicit, one...
Now-a-days reducing the power consumption of the device is the most important factor in VLSI design. This paper deals with the low power, full voltage swing BCD addition using Gate Diffusion Input cell. The average power of proposed BCD adder is 10.2793 μWatt which is compared with the average power of conventional BCD adder and the average power of conventional BCD adder is 50.4721 μWatt. So the...
The interest for ultra-low power integrated circuits in the recent past has guided the research community to establish the proposal of several adiabatic logic circuits in which the energy stored can be efficiently recycled. Many of these architectures suffer from problems like glitch & huge number of transistors as compared to conventional CMOS, which stop them to be used in practical scenario...
In super-threshold regime, a plethora of adiabatic logic styles are reported for ultra-low power design. In this paper a comparative analysis of transistor based imperative logic styles are analyzed in the sub-threshold regime for the first time in the literature. A uniform test bench is set up for fair comparison. Extensive CADENCE simulations were done using 22nm technology file to analyze the effect...
This paper focuses on and analysis and design of current starved voltage controlled ring oscillator. The analysis includes effect of delay time, phase noise, layout area, technology etc. on the frequency of oscillation at various power supplies and control voltages. The simulation results shows that the circuit has higher tuning range and low power consumption suitable for various application domains...
The speed of any processor largely depends on the cache memory that it incorporates and the cache memory is predominantly made up of Static Random Access Memory (SRAM) cells. Therefore, with the technology shrinking every year, it is becoming essential to improve its reliability. This paper presents a qualitative analysis of a 6T Static Random Access Memory (SRAM) cell when it has been induced with...
This paper introduces a new design methodology for high-frequency resonant dc-dc converters utilizing the recently proposed impedance control network (ICN) converter architecture. This design methodology guarantees zero voltage switching (ZVS) and near zero current switching (ZCS) of all transistors across the entire operating range of the converter. As compared to previous ICN converter design techniques,...
This paper proposes the implementation of a serializer in positive feedback source-coupled logic (PFSCL) style. Two realizations for the PFSCL serializer are put forward. The first one is based on the conventional NOR based approach while the fundamental cell based approach is applied in the second one. The functionality of the proposed serializers based on the two approaches is verified through SPICE...
This paper presents a new design and implementation of a power-optimized Pseudorandom Clock Generator (PRCG) for compressive sampling applications. A Pseudorandom Number Generator (PRNG) is utilized to produce uniformly distributed random numbers which select pseudorandom clock frequencies provided by a matrix of non-uniform ring oscillators. The power fed to the ring oscillators is optimized via...
This paper is devoted to the creation of a new logic element that implements the system logic functions in field programmable gate arrays. Proposed LUT that implements the system logic functions M — DC-LUT. Evaluated the complexity of the classical LUT, compared with DC-LUT. Produced simulation of the proposed logic cells DC-LUT for the realization of systems of logical functions in the system simulation...
This paper presents an alternative to crystal based oscillators for reference frequencies in highly integrated SoCs. The frequency reference through the usage of an active bias controlled ring oscillator operating with a supply voltage from 300 to 500 mV for an temperature from −40 to 125 ° C. The oscillator shows a very good temperature and supply voltage frequency stability coming from the active...
This paper proposes a modified positive feedback adiabatic logic (MPFAL) for ultra-low power circuits. MPFAL is based on positive DC voltage range 0.1 to 0.3 V. Half-adder and 1-bit full-adder incorporating this technique also been considered in this work. Comparison shows that average power is reduced in case of modified technique compared to positive feedback adiabatic logic (PFAL) for frequency...
In this paper, implementing for double edge triggered flip flop is introduced. The double edge triggered flip flop is used to reduce number of clocked transistors in the design. The effective method of the double edge triggered paradigm and n-MOS transistor logic of the new proposed implicit pulsed double edge triggered flip-flop (PIPDETFF) is proposed. The power aware technique of the sleep and sleep-bar...
We present Duplex random tree search, an algorithm to optimize performance metrics of analog and mixed signal circuits. Duplex determines the optimal design, the Pareto set and the sensitivity of circuit's performance metrics to its parameters. We demonstrate that Duplex is 5× faster than the state-of-the-art and finds the global optimum for a design whose previously published result was a local optimum...
This paper makes a critical investigation of six programmable delay-producing elements used in present day technology. In signal processing applications, these circuits are capable of incorporating a fixed duration of delay, while keeping the signal integrity intact as well. This comparative study among the six delay-producing elements aids the design engineers in selecting an appropriate delay generating...
This paper presents a complete energy optimized sub-threshold standard cell library exploiting unbalanced pull-up/down (PU/PD) network, logical effort and inverse-narrow-width (INW) techniques. Individual logic cell is optimized for ultra-low-energy applications with low-to-moderate speed requirement. Three 14-tap 8-bit FIR filters are fabricated using a 0.18-µm CMOS technology, while one of them...
Various electronic circuits require a trigger pulse to initiate their operations. Circuits capable of producing very precise duration pulses can be utilized to trigger such circuits. Different designs of trigger pulse generator (TPG) circuit realized by employing optimal delay element (DE) and an XOR logic gate have been reviewed in this work. Profound study of programmable and non-programmable DEs...
Demand for low power circuits is increasing and an easy way to meet low power requirement is to scale down the supply voltage. When the power supply is less than the threshold voltage of the transistors, the circuit is said to be operating in the subthreshold region. This work presents a novel 9T subthreshold SRAM cell. Some important features of the proposed design are employment of single-ended...
A neuron-MOS-based dynamic circuit scheme with two-phase clocks for realizing voltage-mode quaternary logic, is proposed. The dynamic quaternary inverter and literal circuits are designed, and the standard CMOS process with a 2-ploy layer is adopted without any modification of the thresholds. In the proposed circuits, the problem of floating output nodes is solved. The proposed circuits have some...
In recent years, there have been lots of research developments done in face recognition systems. Face recognition systems are widely used for access control, border control, surveillance and in law enforcement. Among other biometrics, it is the most natural and acceptable way of identifying an individual. Face recognition system does not require physical interaction with the user. Research is still...
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