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A highly digital, low-power, forwarded clock transceiver is presented. It employs source shunt terminated transmit driver and all-digital delay line based I/Q generator based clock deskew suitable for fast wakeup, low-voltage operation. A quad-lane test chip fabricated in 22nm CMOS process operates between 3-to-8 Gbps over a FR4 channel with 12dB loss and achieves BER<10−12 while consuming 385-to-790fJ/b.
A 16-core voltage-stacked IC integrated with a switched-capacitor DC-DC converter demonstrates efficient power delivery. To overcome inter-layer voltage noise issues, the test chip implements and evaluates the benefits of self-timed clocking and clock-phase interleaving. The integrated converter offers minimum voltage guarantees and further reduces voltage noise.
A 7 ps/LSB, 0.02 mm2 and 3.9 mW@50MHz Time to Digital Converter architecture with novel MIMO spatial oversampling method is proposed as part of an effort to implement an all-digital PLL (ADPLL) by replacing the phase frequency detector in phase locked loops (PLL). Multiple ring oscillators with unique and variable frequencies are used in order to make N independent measurements of the time pulse to...
This paper presents some of the issues of signal and power integrity in relation with appropriate modeling and simulation methods that are available. The clock signal of a communication protocol is experimentally tested in order to find the rules to improve its signal integrity (SI) along the paths on the printed circuit board (PCB). The signal and power integrity of this PCB are improved using a...
Noise coupling and time interleaving are effective methods for expanding the bandwidth of the low-power wideband delta-sigma modulators. In this paper, a discrete-time ΔΣ modulator topology with these two technologies, combined with shifted loop delays, is proposed. Noise coupling and time interleaving between the two channels enhance the effective order of the noise shaping function. Shifting the...
The nano-injection sensor is a new approach towards high-sensitivity short-wave infrared photon imagers. It resolves the conflict of requiring a large area for high quantum efficiency and small area for high fidelity by using a relatively large micron-scale absorbing volume, and nano-scale sensing elements, which regulates the electron flow and amplifies the signal. The front-end electronics for the...
We1 present an analog front end for a PAM-4 clock and data recovery circuit designed in 65nm CMOS. The front end consists of an arrangement of 8 interleaved master and slave sample-and-hold circuits, to be followed by an array of dynamic comparators. Each interleaved channel contains two wideband buffers with accurate bias and common-mode control circuitry to drive the sample-and-hold circuits. The...
Time-to-digital converters are an attractive topology for quantization because they rely on mostly digital blocks that benefit from scaling of transistors. Time-to-digital converters inherently need a time-domain input, but the input to analog-to-digital converters is primarily in the voltage-domain. Therefore, a voltage-to-time converter is necessary to use time-to-digital converters in analog-to-digital...
The characterization of a hysteretic system response to noise is a challenging problem due to the complexity of the non-Markovian process found as the system output. The recent development of the mathematical theory to describe stochastic processes defined on graphs has provided the framework to analytically calculate the noise spectral density for Preisach hysteretic models [1]. Numerical simulations...
Clock jitter is a crucial factor in high speed and high performance Analog-to-Digital Converter (ADC) testing. Random clock jitter increases the noise floor in the ADC output spectrum making it difficult to obtain the true ADC Signal to Noise Ratio (SNR). Periodic Jitter generates spurs in the ADC output spectrum. Another well-known challenge is to achieve precise coherent sampling. This paper proposes...
This paper covers the design of dynamic element matching algorithms for the compensation of output level mismatch in the internal DAC of a ΣΔ modulator. This issue is considered from the definition of the algorithm itself, down to the design at the transistor level in a scaled CMOS technology. Indeed the main focus of the paper is to demonstrate that the hardware complexity is a major element to be...
In this paper, the authors propose an on-die power supply noise measurement system for power integrity characterization using one bias supply. The measurement system is operated by the bias voltage provided to logical blocks such as Core and IO block in a microprocessor since another supply power rail for the measurement system can create a coupling to the existed power rails. The power supply noise...
This paper presents the design of a fast-settling reference voltage buffer (RVBuffer) which is used to buffer the high reference voltage in a 10-bit, 50 MS/s successive approximation register (SAR) ADC implemented in 65 nm CMOS. Though numerous publications on SAR ADCs have appeared in recent years, the role of RVBuffers in ensuring ADC performance, the associated design challenges and impact on power...
In this paper, two approaches to mitigating the impact of DAC mismatch on the performance of continuous-time Delta-Sigma modulators are presented. The first approach equals an optimized analog calibration which provides better robustness to disturbances of the calibration signal. The second approach, a new dynamic element matching technique labeled clock frequency modulation, modulates mismatch dependent...
BandPass Sampling (BPS) realizes frequency down-conversion in radio receiver front-ends by a sampling rate that can be slightly larger than twice the information bandwidth compared to twice the highest frequency for traditional LowPass Sampling (LPS). However, some implementation problems, harmful signal spectral folding, noise aliasing and sampling jitter, are unavoidably present in conventional...
The paper deals with the analytical performance of the single-cycle detector, which is based on the cyclostationary properties of the signal to be intercepted. The Receiver Operating Characteristics (ROC) are derived theoretically, in discrete time, by using the asymptotic complex normality and covariance expressions of the sample average estimator of the cyclic-covariance when some "mixing conditions"...
In wireless acoustic sensor networks (WASNs), clock synchronization is crucial for multi-microphone signal processing, since clock differences between capturing devices will cause signal drift. This in turn severely degrades the performance of multi-microphone signal processing. After a theoretical analysis of the effect of clock synchronization, we evaluate the use of three different clock synchronization...
Global Positioning System (GPS) carrier-phase (CP) time transfer, as a widely accepted high-precision time transfer method, frequently shows a data-batch boundary discontinuity of up to 1 ns, because of the inconsistency of the phase ambiguities between two consecutive data batches. To eliminate the data-batch boundary discontinuity, several techniques have been proposed in recent years. The question...
This paper proposes an estimator for refining the inaccurate positions and clocks of the anchors during the localization and synchronization of a sensor node in a wireless sensor network. It solves the highly nonlinear problem in closed-form through parameter transformation and multi-stage weighted least squares processing. Theoretical analysis and simulation studies show that the proposed estimator...
Mitigating switching noise in highly complex integrated circuits (ICs) is one of the challenging issues in current design flows. The common way to optimize the noise characteristics is to apply current shaping techniques, which introduce clock skew to distribute the switching activity of the circuit. However, this is typically done at late backend design stages, i.e., in layout after cell placement,...
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