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This paper presents a high speed parallel segmented capacitive DAC that is implemented in a 10-bit 150MSample/s successive approximation register (SAR) ADC. Compared to converters that use the conventional structure, the speed of converting one bit digital code can be 4 times faster while the power remains relatively low. In the switching procedure, a small capacitor array is used to determine the...
We present a 200 MS/s 2x interleaved 14 bit pipelined SAR ADC in 28nm digital CMOS. The ADC uses a new residue amplifier for low noise at low power, and incorporates interleaved channel time-constant calibration. The ADC achieves a peak SNDR of 70.7 dB at 200 MS/s while consuming 2.3 mW from an 0.9 V supply.
A 210 MS/s dual-channel 12-bit analog-to-digital converter (ADC) employing a pipelined successive approximation (SAR) architecture is presented. The ADC is partitioned into 3 stages with passive residue transferring between the 1st and the 2nd stages and active residue amplification between the 2nd and the 3rd stages. The ADC consumes 5.3 mW from a 1-V supply and achieves an SNDR of 63.48 dB at a...
Recent publications have demonstrated ADCs with ENOB > 11, sampling frequencies > 50MHz, with power < 50mW, making the SAR ADC architecture an attractive alternative to the traditional pipeline. This paper presents a production quality 11.5 ENOB, 89dB SFDR, 100MS/s SAR ADC that, including the voltage reference and digital calibration circuitry, consumes 8mW and uses 0.1mm2 in 28nm CMOS. It...
This paper presents an ultra-low voltage and power efficient 10-bit hybrid successive-approximation register (SAR) analog-to-digital converter (ADC). To reduce the total amount of capacitance and relieve requirement of comparator, we propose a hybrid architecture composed of coarse and fine conversions by 7-bit SAR ADC and 3.5-bit time-domain quantizer, respectively. Using residue voltages generated...
A highly digital quadrature clock generator using a digital DLL that employs a digital loop filter and digitally-calibrated replica-based regulator is presented. The proposed DLL combines the advantages of both analog and digital loop-filters of conventional architectures to implement a wide-range, energy efficient, highly digital, and high performance quadrature clock generator. To suppress supply-noise,...
Proposed is a two-stage amplifier exploiting recycling current-buffer Miller compensation (CBMC). By reusing the most current-consuming devices in the 1st stage as current buffer, such an amplifier not only can preserve the merits of typical CBMC implementation in creating the beneficial left-half-plane (LHP) zero, but also can avoid the drawbacks of typical CBMC scheme from degrading the power efficiency,...
A 100 Gb/s CMOS transimpedance amplifier (TIA) for high speed optical communication receivers is presented in this paper. The TIA is based on a differential architecture and composed of a regulated cascode block and a differential amplifier with active feedback. It adopts peaking inductors and a capacitive degeneration scheme to increase the bandwidth. The TIA is designed and laid out in CMOS 65 nm...
As CMOS devices scaling down according to the Moore' law, the reliability and stability of circuit become the main challenge for the chip designs in low supply voltage. Markov Random field (MRF) based design methodology presents a new approach to establish high noise-immune structure for low-power circuit design from the viewpoint of energy. We use global mapping to synthesize all two-input functions...
This paper analyzes the impact of clock skew between comparators in a flash ADC, showing that the SNDR penalty introduced by this effect can become significant at high frequencies. To address this issue, a passive resonant clock network is proposed to distribute the clock to the comparators in a flash ADC. The inductive termination of this network serves to resonate out the parasitic and input capacitances...
A third generation of CMOS Active Pixel Sensor (APS) for high and low light imaging (HaLLI) applications is presented. The sensor pixel 128 × 128 array features more feasible and robust circuit design than its predecessors, which allows for remarkable thermal (KTC) noise suppression, bringing the anticipated noise floor below 1e- rms. A new on-focal, column parallel, two phase, Single Slope (SS) 10...
The Multi-finger layout technique has been extensively used in Nano-scale CMOS circuit design due to the increased circuit performance compared to a single finger layout. However choosing a finger width and number of fingers to optimize circuit performance is a challenging problem. In this paper the performance of a 2.4GHz single ended low noise amplifier (LNA) with a fixed total transistor width...
The quest for lower power consumption has led to aggressive supply voltage scaling till near-threshold and sub-threshold regimes. Reliability represents one of the major concerns in these very low voltage conditions. This paper aims to study the occurrence and propagation of transient errors in noise-affected near and sub-threshold CMOS devices. We have performed SPICE simulation campaigns for 65...
In this work an inverted-based low-voltage implementation for continuous-time sigma delta analog-to-digital converters is proposed. The proposed implementation is applied to a third-order single loop modulator. The loop filter is implemented using active RC integrators. A 50 dB SNDR is achieved for a signal bandwidth of 2 MHz and sampling frequency of 100 MHz, while consuming 1 mA from 0.75 V, supply...
Power supply currents of CMOS digital circuits partly flow through a silicon substrate in their returning (ground) paths. The voltage bounce due to the substrate currents is seen wherever p+ substrate taps on a p-type die and regarded as a substrate noise. An on-chip waveform monitor confirms the side-channel leakage on the silicon substrate from an AES cryptographic module in a 65 nm CMOS demonstrator...
Dynamic logic style is used in high performance circuit designs due to its high speed. But during cascading of dynamic gates, problem arises due to charge sharing, charge redistribution and charge leakage. To avoid these problems, domino logic design is used in the circuit due to their advantages such as their high speed and less noise immunity. In this paper we have proposed a new domino circuit...
Low noise amplifier (LNA) performs as the initial amplification block in the receive path in a radio frequency (RF) receiver. In this work an ultra-wideband (UWB) 3.1–10.6-GHz LNA is discussed. By using the proposed circuits for RF CMOS LNA and design methodology, the noise from the device is decreased across the ultra-wide band band. The measured noise figure is 2.66 −3 dB over 3.1–10.6-GHz, while...
In this paper, a new pole-zero technique for reducing thermal noise is represented. In the proposed new pole-zero method, by extracting the noise and voltage-gain equations of the amplifier, the zeros of the noise transfer function (TF) are managed, so that they are placed near the poles of the gain TF. Therefore, significant noise reduction is achieved in the condition of maximizing the small-signal...
In this paper a highly linear differential CMOS low noise amplifier (LNA) for ultra-wideband (UWB) applications is proposed. The proposed LNA uses a linearization technique to improve both input second- and third-order intercept points (IIP2 and IIP3), simultaneously. The linearity is improved by canceling the common-mode part of all intermodulation (IM) components from the output current. Analysis...
In this paper, an accurate and computationally efficient model for millimeter wave frequency signal and noise performance of MOSFETs is proposed. This model is based on the transmission-line and distributed behavior of the transistor along the electrodes width. The model is verified by comparing with the conventional lumped model. Furthermore, the proposed model is used to design a CMOS LNA operating...
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