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An inductorless wideband LNA is designed with low NF and high linearity. It is based on the use of both passive and active feedback with current reuse techniques to achieve the required low NF, high BW, and suitable gain. An auxiliary transistor is added to the differential implementation to achieve a high linearity. The circuit is designed in 0.13µm TSMC technology and exhibits a gain of 18.4dB over...
In this paper, a power reduction technique for wideband common gate low noise amplifiers (LNA) is proposed for low power application. Stacked current reused complementary capacitive cross coupling (CCCC) concept is proposed to improve LNA power efficiency. As a proof of the concept, the improved broadband differential common-gate LNAs (CG-LNA) designed in 0.18µm CMOS technology. The LNA achieves a...
We present the design and characterization of a broadband, low-noise transimpedance amplifier (TIA) with adjustable gain-peaking, implemented in 65-nm CMOS. The TIA exhibits 40-GHz bandwidth, 20-dB gain and consumes 107 mW power. An additional continuously-tunable 12-dB gain-peaking near 40 GHz is available through a simple yet effective tuning mechanism, consuming only 14% more power. The adjustable...
This paper presents the design and characterization of a high gain, high-speed differential transimpedance amplifier (TIA) to be used as the front-end interface for optical receiver applications. The TIA is realized in a standard 0.18-µm digital CMOS technology and it dissipates 25.4mW from a single 1.8 V supply. The objective of the design is to maximize the bandwidth. The main contribution of this...
An area-efficient and low-power low-noise amplifier with adjustable parameters for bio-potential recording applications is presented. This amplifier replaces traditional analog filters using large AC coupling capacitor with the proposed DC offset suppression block based on Differential Difference Amplifier (DDA) structure, which allows the system to obtain good high pass characterization without using...
In this paper, a low-noise CMOS readout front end for biopotential acquisition applications is presented. The proposed circuit, implemented using 130 nm standard CMOS process, has a thermal noise floor of 10 nV/√Hz, a corner frequency of 300 mHz, and dissipates 3.2µW of power when powered using a 1 V supply. The designed circuit occupies a die area of 0.007mm2 and thus renders itself as an excellent...
This paper presents a 128.7nW analog front-end amplifier and Gm-C filter for biomedical sensing applications, specifically for Electroencephalogram (EEG) use. The proposed neural amplifier has a supply voltage of 1.8V, consumes a total current of 71.59nA, for a total dissipated power of 128nW and has a gain of 40dB. Also, a 3th order Butterworth Low Pass Gm-C Filter with a 14.7nS transconductor is...
With growing applications and increased integration of functionalities on multi-electrode biosensors, more attentions are paid to the need to include on-chip temperature measurement for providing ambient temperature monitoring of bio-samples and for recording heat generated by biosensor chips and their potential damage to bio-samples. This paper presents an integrated temperature sensor design which...
This article presents a variability resilient CNFET based 10T S RAM cell. Critical design metrics of S RAM cells are estimated using Monte-Carlo simulations and compared with that of conventional Si-MOSFET based 10T S RAM cell. The CNFET based SRAM cell offers 3.15× and 1.98× improvements in Read Access Time (TRA) and Write Access Time (TWA) respectively. The proposed bit cell also offers 1.94× and...
This paper presents the design and simulation of High gain Source degenerated Cascode LNA for Wi-max and W-CDMA applications at 3.5GHz. The design uses an enhanced cascade topology to attain improved forward gain and noise figure. Th is design includes lumped elements like inductor, capacitor and resistors to design input and output matching networks. The targeted narrow-band gain, impedance matching...
This paper reports on the world's first CMOS low noise amplifier (LNA) operating successfully on a radio telescope since October 15th, 2010. The radio telescope used in this work is the Synthesis Telescope operated by the Dominion Radio Astrophysical Observatory, NRC, and located near Penticton, BC, Canada. This paper describes the work that led to the installation of the LNA on the telescope and...
Devices fabricated through TSMC 0.18 micron CMOS process are modeled and implemented in Agilent ADS for the circuit designs. Two low-noise, well impedance-matched radio frequency amplifiers working at various nearby center working frequencies, 2.6 GHz and 2.8 GHz, are proposed using Class-E power amplifier mechanism. Both are deliberately put in series such that both can couple with each other, The...
This paper describes a CMOS interface circuit for silicon photonics. 20-Gb/s operation of an optical receiver front-end circuit is demonstrated using an optical signal applied to the optical front-end. The transimpedance amplifier (TIA) is based on an inverter with resistive and inductive feedback for low power consumption and frequency compensation. A negative capacitance generation is employed in...
This paper describes a new capacitor sharing technique for pipeline ADCs. It enables power reduction of the first and second MDACs simultaneously. The presented noise and power analysis shows that the proposed method is about 30% more efficient than the conventional one in terms of the first and second MDACs power dissipation. A 10-bit 40MS/s pipeline ADC employing the proposed technique was designed...
We present a 1-GΩ CMOS transimpedance amplifier (TIA) suitable for processing sub-nA-level currents in electrochemical biosensor signal-acquisition circuits. Use of a two-stage active transconductor provides resistive feedback in place of a single large-area linear resistor. We engineer the TIA feedback loop to suppress output offset caused by dc input leakage currents of ±0.9 nA. We also implement...
A very simple power supply rejection ratio (PSRR) enhancement technique is presented. It is suitable, among others, for low voltage power low power (LVLP) DC circuits such as biasing circuits. It is shown that a high insensitivity to AC noise in supply rails can be achieved with an almost zero contribution to the total internal noise. This is achieved at the expense of very small additional circuitry...
In this paper, an extra loop delay compensation technique for hybrid delta-sigma modulators (DSM) is proposed. The hybrid DSM replaces analog components with digital circuitry by carrying out A/D conversion in the middle stage of a loop filter. The hybrid DSM is a small-sized prototype that realizes A/D conversion with low power consumption. In many cases, A/D converters exhibit latency, which becomes...
This paper presents a design and technique for low noise, low offset modulation demodulation circuit for chopper stabilized amplifiers use in CMOS-MEMS sensor applications. In these sensors, where the sensed signals are usually very weak, a low-noise interface readout circuit plays a crucial role in determining the overall sensor performance and success in the market. Amplifiers are the core building...
Design of tunable multi-band time delay elements based on frequency translation is presented. The proposed topology exhibits time delay of multiple periods of the RF carrier. Two possible implementations of the proposed idea are presented and simulation results are shown for one such implementation. The implemented circuit exhibits an envelope delay of 2.5 ns with the RF carrier delay tunable from...
This paper presents a multi-bit, continuous time delta-sigma modulator with 20 MHz bandwidth implemented in 65nm CMOS for cellular communication. The modulator features a third order, single loop filter and a 4-bit internal quantizer operating at 640 MHz. The DACs are resistive for lower thermal noise compared to the current-steering DACs and nonreturn-to-zero DAC pulse is used to reduce the clock...
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