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The Characteristic Basis Function Pattern Method (CBFPM) is applied to compensate for pattern variations that result from surface inaccuracies in a dual-reflector antenna system. Toward evaluating the efficiency of this pattern modeling technique in a realistic environment, the impact of noise in calibration measurements required to solve for the pattern model, as well as that of calibration measurements...
This work studies the problem of blind sensor calibration (BSC) in linear inverse problems, such as compressive sensing. It aims to estimate the unknown complex gains at each sensor, given a set of measurements of some unknown training signals. We assume that the unknown training signals are all sparse. Instead of solving the problem by using convex optimization, we propose a cost function on a suitable...
This paper presents the design of a second order double-sampling split path Sigma Delta modulator with cross noise-coupling. The power budget for the double-sampling is reduced by using bilinear integrators, while cross noise-coupling between the two modulator loops increases the noise shaping to third order. The implementation of the noise-coupling is incorporated into the second integrator using...
A reconfigurable 65nm continuous-time low-pass ΔΣ modulator operates with a sampling frequency from 491 MHz to 1536 MHz, a signal bandwidth from 10MHz to 100 MHz, and a dynamic range of 75.4dB to 62.8 dB, respectively. Reference shuffling in the flash ADC is used to improve the linearity of the flash and DAC, while also increasing the highest sampling rate and bandwidth of the modulator.
This paper reviews different mechanisms of saturation in SIS mixers and presents results of the modeling and experimental verification of the proposed solution to increase the saturation level by de-tuning the SIS mixers, to allow solar observations with ALMA.
So far almost all wide-band (>10MHz) continuous-time ΣΔ ADCs use active-RC filters. Although this type of filter possesses excellent linearity, it behaves as a resistive load for the preceding stage, which requires a signal buffer. For high speed and high resolution applications, a low noise and low distortion signal buffer consumes quite large power. Gm-C filters have small capacitive loads, which...
Modern CMOS technologies provide digital signal processing capabilities at high integration density and low energy per operation. Hence, expending digital resources to enhance performance-limiting analog building blocks has become a widely explored paradigm in modern ICs. This paper reviews the state-of-the-art in digitally assisted data converter design and provides an overview of commonly used techniques.
This paper presents a dynamically latched threshold configurable comparator to eliminate the DAC in conventional SAR ADC designs. The comparator uses intentional circuit asymmetry to generate precise threshold or offset voltages. Four offset stages with resolutions of 15.5 μV, 316 μV, 7.9 mV and 29.85 mV are superimposed to yield a 282.6 mVpp tuning range. The high resolution is obtained by exploiting...
A two-stage pipelined ADC employs a double-sampling residue amplifier, two interleaved precharged DACs, and a new calibration scheme to correct for residue gain error, offset, and nonlinearity. Realized in 65-nm CMOS technology and sampling at 1 GHz, the prototype exhibits an FOM of 25 fJ/conversion-step while drawing 7.1 mW from a 1-V supply.
This paper describes design techniques for Bipolar and BiCMOS analog circuits. Comparison on such performances as transconductance, speed, matching, noise of bipolar and CMOS transistors are reviewed and compared. Design achievements such as a single core 12 Bit 1.5GS/s Analog to Digital Converter (ADC) [1] and a single core 12 Bit 3GS/s Digital to Analog Converters (DAC) [2] based on a fully bipolar...
As the GPS signal simulator is applied more and more extensively, the test equipment of the GPS signal simulator is required higher and higher. Currently, the calibration using the standard instrument is the most important means, which severely restricts the test environment of the simulator. In order to meet the test requirements of the GPS signal simulator for diversified situation, this paper proposes...
This paper addresses the application of missing data recovery via matrix completion for audio sensor networks. We propose a method based on Euclidean distance matrix completion for ad-hoc microphone array location calibration. This method can calibrate a full network from partial connectivity information. The pairwise distances of microphones in close proximity are estimated using the coherence model...
The paper deals in short with the various algorithms useful in determining the pitch distances of a linear scale. The main advantages and drawbacks from the point of our application are summarized. The environmental and distortional influences are discussed and some computational aspects are given.
A monolithic accelerometer design with zero-g calibration with TSMC 0.18 μm mixed-signal 1P6M process is presented. On-chip digital offset calibration enables compensation of random mechanical offset in the sensor due to process variation. The maximum 21 fF capacitance mismatch can be calibrated. The simulation results show that the whole system have 452.1 mV/g sensitivity. The power consumption is...
This work develops an integrator-leakage calibration technique for the switched-capacitor integrators in a delta-sigma modulator (DSM). Integrators that are realized with low-gain opamps are lossy. A DSM that uses lossy integrators exhibits a degraded signal-to-quantization-noise ratio. In the calibration of an integrator, its integration leakage is determined in the digital domain, and the leakage...
This paper describes the design and the performance of a virtual simulation environment to evaluate a machine vision based pose estimation system used for the general problem of satellite servicing. The vision system features a wide angle monocular camera to track the interface ring of a non-cooperative satellite using ellipse extraction. The effects of the camera parameters and of the relative camera-satellite...
A relatively low-power 16-bit 1MS/s successive approximation register (SAR) analog-to-digital converter (ADC) is presented in this paper. Based on the typical structure of SAR ADC, some effective techniques including bootstrapped sampling-switch used to suppress nonlinear distortion, dynamic comparator to reduce power dissipation and the offset-calibration to ensure conversion accuracy have been employed...
The Scheimplug condition consists on tilting the image plane (CCD plane) respect to the lens plane in order to increase the depth of field of a camera. The problem with this kind of cameras is that the conventional calibration methods doesn't take into account the introduced angle between the image plane and the lens plane. Only if the angle (from now on Scheimpflug angle) is small, the tangential...
Impairments between ADCs are known to severely limit the resolution and bandwidth of time-interleaved (TI) architecture. This paper proposes a general framework describing simultaneously the gain, time-skew, bandwidth and offset mismatches. Statistical laws are analytically derived. They convert SFDR specifications into matching requirements and therefore provide key rules for TI-ADCs designers.
In this paper, we present an elegant solution to the 2D LIDAR-camera extrinsic calibration problem. Specifically, we develop a simple method for establishing correspondences between a line-scan (2D) LIDAR and a camera using a small calibration target that only contains a straight line. Moreover, we formulate the nonlinear least-squares problem for finding the unknown 6 degree-of-freedom (dof) transformation...
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