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We present a fully-digital digital-to-analog converter (FD DAC) architecture design for high-speed communication systems. The FD DAC design is based on the ΔΣ modulation. The specifications for the DAC includes a low 1.2 V supply voltage, a high 5 GS/s input sampling rate, and a wide 2.5 GHz bandwidth. We employ a combination of the time-interleaving, parallel, and pipelining techniques to reduce...
In this paper, an extra loop delay compensation technique for hybrid delta-sigma modulators (DSM) is proposed. The hybrid DSM replaces analog components with digital circuitry by carrying out A/D conversion in the middle stage of a loop filter. The hybrid DSM is a small-sized prototype that realizes A/D conversion with low power consumption. In many cases, A/D converters exhibit latency, which becomes...
This paper presents a design and technique for low noise, low offset modulation demodulation circuit for chopper stabilized amplifiers use in CMOS-MEMS sensor applications. In these sensors, where the sensed signals are usually very weak, a low-noise interface readout circuit plays a crucial role in determining the overall sensor performance and success in the market. Amplifiers are the core building...
In this work, an unscented Kalman filter with improved numerical properties is shown to be able to simultaneously estimate the major nonidealities of continuous-time sigma-delta modulators. Circuit imperfections in sigma-delta modulators like, e.g., nonlinearities in the feedback digital-to-analog converters are known to highly reduce the modulators's performance. The state of the art shows several...
This paper presents a multi-bit, continuous time delta-sigma modulator with 20 MHz bandwidth implemented in 65nm CMOS for cellular communication. The modulator features a third order, single loop filter and a 4-bit internal quantizer operating at 640 MHz. The DACs are resistive for lower thermal noise compared to the current-steering DACs and nonreturn-to-zero DAC pulse is used to reduce the clock...
A discrete-time, switched-capacitor, MASH 2–2 4th order ΣΔ modulator, clocked with frequency of 1 GHz, was designed in a 65 nm CMOS technology. This modulator uses passive integrators based on the ultra-incomplete settling (UIS) concept. Electrical simulations show that the modulator achieves a peak SNDR of 66.8 dB, a peak SNR of 67.7 dB, an ENOB of 10.8 bits and DR of 70dB for a signal with a bandwidth...
As a signal detection method for multiple-input multiple-output (MIMO) communications, this paper proposes multi-stream constrained search (MSCS) that achieves very good trade-off between computational complexity and bit error rate (BER) performance. The proposed method sets a minimum mean-squared error (MMSE) detection result to the starting point. From this point, MSCS searches for signal candidates...
This paper proposes a novel approach for data-compression using Delta-sigma modulator (ΔΣ-M) and applies it to design bit-stream based controllers. An adaptive scheme is introduced to automatically determine the upper and lower boundaries of the quantizer of the ΔΣ-M. The stability condition of the feedback control system with embedded ΔΣ-M is derived analytically based on sliding mode analysis. The...
In this paper, we describe an experimental evaluation platform, which enables us to obtain the performance of baseband modulation techniques for usage in Visible Light Communication (VLC) applications. For the demonstration of the evaluation platform, we have chosen for Manchester encoding. This choice is exemplary, the described system is able to deal with a large set of analog and digital modulation...
Nanonetworking indicates new solutions for many applications in biomedical and industrial fields. In this paper, we examine the diffusion-based molecular communication for information transmission in nano-networks. Design of practical decoders for resource-limited nano-networks requires an understanding the fundamental performance limits of memory-limited decoders. While some existing works in the...
In this work an inverted-based low-voltage implementation for continuous-time sigma delta analog-to-digital converters is proposed. The proposed implementation is applied to a third-order single loop modulator. The loop filter is implemented using active RC integrators. A 50 dB SNDR is achieved for a signal bandwidth of 2 MHz and sampling frequency of 100 MHz, while consuming 1 mA from 0.75 V, supply...
We discuss techniques for measuring the correlation between phase-modulated (PM) and amplitude-modulated (AM) noise in an oscillator and report results of such correlation in a few selected oscillators of similar size, weight, power consumption and vibration sensitivity.
Multipath spread is one of the most important factors which limit data transfer with high bit rate. Data transfer with high bit rate is possible in the range of gigahertz. The main problem in this frequency range is multipath spread. Orthogonal frequency division multiplexing (OFDM) technique divides the transferring symbols between several subcarriers and transfers them simultaneously. Accordingly...
A novel strategy of zero optimization in cascaded ΣΔ modulators is presented. In the proposed structure, by using just an analog inter-stage feedback path, one pair of the noise transfer function (NTF) zeros is distributed over the desired bandwidth so that the in-band quantization noise is reduced. The effectiveness of the proposed modulator is verified by analytical calculations and simulation results.
This paper presents a new digital method to improve the performance of the ΔΣ modulator. The proposed method uses a fuzzy line enhancer (FLE) to reduce the existing noise in the output of the modulator. The simulation results show 14 dB improvements in signal to noise and distortion ratio (SNDR) by using the FLE.
In this paper, we propose two novel receiver designs for asymmetrically clipped optical orthogonal frequency division multiplexing (ACO- OFDM). The first one, termed 'Proposed Receiver I', exploits the structure of the clipping noise which improves the power efficiency over the state-of- the-art ACO-OFDM receiver. The second one, termed 'Proposed Receiver II', exploits the benefit of bit error correction...
In this paper, a CMOS monolithic digitized light detector for light monitoring applications is newly proposed. The proposed chip is attractive due to the fact that analog processing circuits and light sensor are integrated robustly and compactly. The output signal of the proposed chip is a pulse stream, it could be easily sent over a wide range of transmission media, such as PSN, radio, optical, IR,...
Multicarrier communication is a well-known and widely used method in the current wireless or wired data transmission. Orthogonal Frequency Division Multiplexing (OFDM) is the leading technology in this area and is implemented in various forms in almost every current broadband communication systems. It has a number of advantages, but also few significant shortcomings. Especially the high out-of-band...
Investigation of readout electronic dedicated to electromechanical audio sensor is presented. The circuit is able of reading piezoresistive gauge implemented with silicon nanowire (NEMS) and bring electromechanical signal to high-resolution digital output. Low-noise low-power CMOS operational transconductance amplifier (OTA) is presented. The low-noise amplifier (LNA) has been designed in a 0.28 μm...
This article gives a discussion on impulse noise, its models and how it affects communications systems. We discuss the different impulse noise models in the literature, looking at their similarities and differences in communications systems. The impulse noise models discussed are memoryless (Middleton Class A and Bernoulli-Gaussian), and with memory (Markov- Middleton and Markov-Gaussian). We then...
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