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This paper reports the implementation of a high resolution and high dynamic range ΣΔ capacitive accelerometer for navigation applications. Designed system can achieve up to ± 40g full scale range, 131.9 dB dynamic range at 1 Hz, minimum noise floor of 6 µg/√Hz, and bias instability of 6.4µg. Flexible architecture combines the advantages of 2nd and 4th order ΣΔ modulators into a high performance design...
Radiation spectra represent inherently quantization data in the form of stacked channels of equal width. The spectrum is an experimental measurement of the discrete probability density function (PDF) of the detector pulse heights. The quantization granularity of the spectra depends on the total number of channels covering the full range of pulse heights. In analog pulse processing the total number...
Noisy network coding, which elegantly combines the conventional compress-and-forward relaying strategy and ideas from network coding, has recently drawn much attention for its simplicity and optimality in achieving to within constant gap of the capacity of the multisource multicast Gaussian network. The constant-gap result, however, applies only to Gaussian relay networks with independent noises....
This paper proposes a distributed resource allocation strategy for cognitive radio networks based on a swarming model that incorporates random link failures and quantized communications. The swarming mechanism is used to minimize the interference produced by the cognitive users, take advantage of cooperative sensing, avoid collisions among the users and limit the spread of resources in the time-frequency...
A wide-tuning low-cost PLL architecture with negligible loop filter area is presented. To overcome the static phase error or reference spur problem of the conventional type-I PLL over broad frequency tuning range, a Δ-Σ DAC based real-time frequency acquisition aid method is employed in the PLL voltage domain. Different from other Δ-Σ based frequency acquisition methods mainly used for the type-II...
In this paper a 1V 15-bit ΔΣ ADC for audio application is presented. Second order modulator with feed-forward path is adopted in order to reduce the swing of each integrator. Non-linear gain effect is mitigated. Single stage amplifier with high power efficiency is employed to save power. Decimation filter is implemented with seven-stage cascade sub-filters. Timing multiplexing and resource reuse methodology...
This paper presents a dual sampling technique for analog-to-digital converters (ADCs) to convert multi-carrier signals more efficiently and proposes an 11b switched-capacitor pipeline ADC based on this technique. With the dual sampling technique, the input signal power of the ADC can be boosted without getting excessive clipping noise and the ADC can have a higher resolution over the critical low...
Present approaches for predicting the stability of Delta-Sigma (Δ-Σ) modulators are mostly confined to DC inputs. This poses limitations as practical applications of Δ-Σ modulators involve a wide range of signals other than DC such as speech, audio and multiple sinusoids as is the case for synthetically generated speech or audio or any other signal, through the appropriate composition of multiple...
This paper presents an online background calibration technique for eliminating the quantization noise leakage in MASH continuous-time delta-sigma modulators (CT-MASH). By using a system identification approach, the signal and noise transfer functions of each stage in CT-MASH are fully identified. This information is used to adaptively tune the coefficients of the digital noise cancellation filters...
The mismatch-induced fractional spurs have so far limited the adoption of phase-interpolation-based fractional-N PLLs. Only recently a background cancellation technique, embedded in a digital fractional-N PLL, has faced this issue. In this paper, we will show that this technique is equivalent to a multi-path adaptive circuit that cancels the effects of the phase interpolator non-linearity. This analysis...
In the last years the research in the field of digital watermarking evolved toward non conventional watermarking applications, which we refer to as watermark aided audio processing. In this paper, we present some of our contributions to this new concept of watermarking for audio processing, namely doping watermarkand witness watermark. The doping watermarking modifies the statistical characteristics...
A discrete fading channel (DFC) consisting of a binary modulated time-correlated Rayleigh fading channel used in conjunction with coherent soft-decision demodulation of resolution q is considered. The capacity of the binary input 2^q-ary output DFC, which can be explicitly expressed in terms of a non-binary noise discrete channel with stationary ergodic $2^q$-ary noise, is evaluated in terms of q...
This work addresses the problem of joint quantization and power allocation in wireless sensor networks where sensors observe a source, quantize their observations and transmit to a fusion center (FC) which reconstructs the source using linear minimum mean-squared error (LMMSE) estimation rule. The sensors employ scalar quantizers to quantize the observations. We formulate the reconstruction distortion...
Clock timing jitter refers to random perturbations in the sampling time in analog-to-digital converters (ADCs). The perturbations are caused by circuit imperfections in the sampling clock. This paper analyzes the effect of sampling clock jitter on the acquired samples in the midst of quantization noise and random Gaussian noise. The paper proposes a method for estimating the jitter for cognitive radio...
A novel high-order single-loop incremental sigma-delta ADC for multi-channel applications is proposed. High-order continuous-time architectures are explored using a 3rd order single-bit modulator as a test-case. The performance of the proposed architecture, taking into account critical non-idealities, is analyzed and its advantages and issues are discussed. Behavioral simulations show a key advantage...
Wireless neural recording systems require the data-acquisition and signal-processing hardware to be moved to the transmit side. The strict power-density constraints on implanted devices require new ideas for system power minimization. Minimizing the number of bits of the ADC would have a significant impact on the total system power by reducing the power of the ADC, the DSP, and the transmitter. In...
This paper presents a design methodology for dithered bus-splitting Multi stAge noise SHaping (MASH) digital delta-sigma modulators (DDSMs). Rules for selecting the appropriate wordlengths of the constituent DDSMs are derived which ensure that the spectral performance of the bus-splitting architecture is comparable to that of the conventional design but with less hardware. Behavioral simulations are...
This paper presents a new high order cascade sigma delta modulator called GMSCL. It uses first and/or second order modulator with unity signal transfer function in each stage and a global feedback to lower the sensitivity to circuit imperfections, to relax the output swing and gain requirements of amplifiers and to avoid digital prefiltering in the quantization error cancellation logic. The zeros...
This paper proposes a new low order time variant digital ΣΔ MASH modulator for fractional frequency synthesizers. The phase noise spectrum is improved as the spur tones from the fractional modulation are disabled. The usage of low order time variant MASH architectures reduces the number of levels that control the programable divider, reducing therefore the complexity and power requirements of the...
In this paper, we describe a novel error diffusion scheme for higher halftone quality with less visual artifacts. The proposed algorithm improves mid-tone quality of error diffusion significantly by diffusing the error along a jumping scanning path. The algorithm calculates the accumulative error to determine the point where breaks up the scanning path. A cost function is developed to search the optimal...
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