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This paper demonstrates the idea of utilizing Source-Coupled Logic (SCL) concept in dynamic logic realization. The technique gives dual (normal as well as complemented) output. As compared to conventional dynamic logic style, by using the mentioned realization, charge sharing and contention current problems can be avoided to a large extent. The sizing requirement of keepers is not stringent in the...
In response to the requirement of novel crosstalk-reduction scheme for high density through silicon via(TSV) interconnects in silicon interposer, this paper presents a structure and performance analysis of through-silicon via(TSV) with direct ohmic contact between a ground TSV and silicon substrate for coupling mitigation purposes. We further expand the structure to a 3×3 TSV array and investigate...
We derived expressions of power and ground voltage noises for reducing common-mode voltage in a power distribution network of an LSI and found that they have the same amplitude and a phase difference approaching 180°. To confirm this, we performed an experiment using a test board with a cover-metal structure-essentially, a floating conductor in an LSI package to reduce common-mode voltage. The evaluation...
Resonances in power distribution network are the major cause of voltage fluctuation and noise problems. In this paper, a new method that suppresses impedance peak is proposed. The proposed method uses a high series resistance (HSR) capacitor in parallel to regular bypass capacitors. By selecting the parameters so that the series resonance frequency of the HSR capacitor equals to the anti-resonance...
A 460 kS/s 10-bit successive approximation register (SAR) analog-to-digital converter (ADC) with rail-to-rail input range is proposed for acquiring capacitive sensor. The specifications of ADC are optimized at system level, emphasizing the ADC following a switched-capacitor (SC) capacitance-to-voltage converter (C2V). A bootstrap switch with body effect reduction is adopted to provide the rail-to-rail...
Finding a suitable topology and Noise-transfer-function for higher order Incremental Delta-Sigma ADCs is a complex task. Estimating the performance of the ADC taking the circuit nonidealities into account by simulation requires sophisticated modeling and significant computing resources. Even with complex models, taking into account all nonidealities is not possible. This work proposes a completely...
This paper analyzes a method for bandwidth improvement based on a gain-bandwidth boosting technique in transimpedance amplifiers. This method is suitable for visible light receiver front-ends employing large area photodiodes, where open loop voltage gain can be optimized according to the photodiode capacitance. Theoretical results, assuming a two-pole transfer function, are compared with simulation...
A new design procedure is derived for analog design with MOSTs in all three regions of operation i.e. strong and weak inversion and velocity saturation. BSIM6/EKV model parameters are used. Optimum biasing points are derived for single- and two-stage amplifiers. It is shown that for channel lengths around 20 nm, a unique optimum is achieved for the fT × gm/IDS Figure of merit. At such low channel...
We report the noise analysis of a capacitor to voltage converter (CVC) with a zoom-in concept, used as a first stage in capacitive sensor interfaces for measuring very small capacitance variations. We will show that the zoom-in concept introduced in the first stage can not only relax the resolution requirement of the following stages, i.e. an analog-to-digital converter (ADC), but it can also increase...
A high performance eDRAM technology has been developed on a high-performance and low-power 22nm tri-gate CMOS SoC technology. By applying noise reduction circuit techniques and extensive device and design co-optimization on eDRAM bitcell and critical circuits, over 100μs retention time at 95°C has been achieved for a Gbit eDRAM with robust manufacturing yield.
We propose a novel touch panel structure, sensing method, and system which composes a low-cost transparent electrically-conductive thin film with higher Rs than the ITO film by two orders of magnitude. Relatively small number of extraction electrodes is directly attached upon the thin film without any circuit pattern. The proposed panel can realize even the wall tapestry-type touch panel of larger...
Power integrity design has become a critical issue in digital electronic systems, as advanced CMOS LSIs operate at higher clock frequency and at lower supply voltage. Power supply fluctuation excited by core circuits or I/O buffer circuits induces logic instability and electromagnetic radiation. Therefore, total impedance of power distribution network (PDN) must be taking into consideration in the...
A cryogenic and low noise front end has been developed first for T2K experiment. The latest developments are aimed for LAGUNA LBNO, which is a long term neutrino project (year 2020). A middle term detector will be build at CERN in 2015. However, the current design is being mounted on a small Time Projection Chamber (TPC) in our laboratory. The identical channel of this 8-channel chip is made of a...
This paper presents an analytical model for Colpitts oscillator phase noise computation by multi-harmonics Kurokawa method. The circuits parameters adopted in this model are derived by super-position principle presented in poly-harmonics distortion (PHD) modeling approach. In addition two types of noise source: additive noise and frequency converted noise are discussed in detail. Thus the more accurate...
The availability of high-intensity and high repetition rate X-ray sources, like XFEL facilities, impose severe constraints for the detectors to be developed, in terms of high speed and high dynamic range. For the European XFEL, different detector developments are on the way to readout X-ray flashes with a repetition rate of 4.5MHz with a dynamic range up to 104. In this framework, different compression...
The CLARO is an ASIC for single photon counting with pixellated photomultipliers, designed to sustain a high counting rate at low power. It was primarily developed to readout multi-anode photomultipliers (Ma-PMTs) in the upgraded LHCb RICH detectors at the LHC. The first four-channel prototype, named CLARO-CMOS, was realized in a 0.35 µm CMOS technology, demonstrating the capability to count single...
In this work, we present the design and the results of the analog channel of the readout circuit for the outer layers of SuperB Silicon Vertex Tracker (SVT). In these layers, the strip detectors have a very high stray capacitance and high series resistance. Therefore, the noise optimization was the first priority design concern. To fulfill the noise level and efficiency requirements, a compromise...
This paper presents the architecture, simulation and measurement results of a low power dual stage charge sensitive amplifier providing a time-over-threshold analog to digital conversion with linear transfer characteristic dedicated for readout of long silicon strip detectors. The key features of the presented solution are: very low power consumption (2 mW), linear transfer characteristic and low...
Sphinx1 is a novel pixel architecture adapted for X-ray imaging that can detect radiation by photon counting and by charge integration. In photon counting mode, each photon is compensated by one or more counter-charge packets which can be dimensioned at a level as low as 100 electrons and the number of injected counter-charge packets indicates the incoming photon energy, thus allowing a spectrometric...
This paper presents the analysis of timing resolution for a digital silicon photomultiplier (D-SiPM) using a SPICE simulator. A D-SiPM has more than a hundred of pico seconds timing resolution for single-photon detection due to detector jitter, circuit noise and routing skew. Especially, circuit noise and skew depend on the SiPM design strongly. To investigate how single-photon timing resolution is...
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