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We present an FPGA-synthesizable version of a pseudo-random pulse generator that can be used to emulate radioactive source activity. It is intended for debugging real-time digital pulse processing applications, beyond the capabilities of periodic generators. The proposed module delivers a discrete random sequence that follows the Poisson inter-arrival distribution. Operation is based on a barrel-shifted...
This paper presents a new design and implementation of a power-optimized Pseudorandom Clock Generator (PRCG) for compressive sampling applications. A Pseudorandom Number Generator (PRNG) is utilized to produce uniformly distributed random numbers which select pseudorandom clock frequencies provided by a matrix of non-uniform ring oscillators. The power fed to the ring oscillators is optimized via...
Since decades, orthogonal frequency division multiplexing (OFDM) has been drawing its attention in the area of wireless and satellite communication systems such as IEEE 802.11 a/g/n, ADSL, WiMAX and DVB-T/SH. In these applications, OFDM has drawbacks of high Peak-to-Average Power Ratio (PAPR) and Inter carrier symbol interference (ISI). Recently, Carrier Interferometry OFDM (CI-OFDM) as an alternative...
A new time-to-digital converter (TDC) for the time-of-flight measurement (TOF) architecture using a cyclic method and time amplifier (TA) with three level conversions is proposed. To increase the input range of the TDC and protect it from PVT variations, the cyclic method and DLL architecture are used in a second-level conversion. The third conversion calculates the residue remaining after the second...
Early design space exploration has been shown to be an important factor in reducing the development time for Network on Chips. In this paper, we present a Matlab toolbox aimed at the early-stage design space exploration for NoC router design, the router founding element of a NoC. The toolbox is based on the discrete event simulation engine SimEvents. The presented toolbox can be used to graphically...
The transition from 2D to 3D Network on Chips is have recently gained momentum with research effort targeted to solving the different implementation issues. The planification and design space exploration for 3D NoCs, intuitively harder than for 2D NoCs, calls for more flexible and powerful simulation tools. The Matlab ecosystem is appropriate for the implementation of such simulation systems. In this...
Planning and evaluating a Network on Chip (NoC) for a specific application is usually a complex task that requires the collaboration of both hardware and software specialists. Predicting the performance of the devised architecture and solution is both difficult in nature and time consuming. In this paper we present a high level model for five-port router based NoCs using Matlab's SimEvents toolbox...
This paper describes the design, implementation and analysis of FPGA based High Frequency Switching Sinusoidal Pulse Width Modulation (SPWM) generator for the application of three-phase DC/AC inverters using Pipelined CORDIC algorithm. The carrier frequency of up to 4 MHz and operating frequency of 256 MHz is achieved. The switching frequency can be dynamically reconfigurable on real time by the user/external...
Analog to Information Converter (AIC) is the heart of an energy efficient bio potential acquisition system using compressed sensing (CS) technique. This paper presents the design and implementation of AIC. Charge redistribution Digital to Analog Convertors (DAC) is used for power and area efficiency. A successive approximation register (SAR) control logic and dynamic latch type comparator are used...
CRC (Cyclic Redundancy Check) is a simple and an elegant method for error detection. It finds application in most of the high-speed data communication protocol. In High Energy Physics experiment often CRC is used for control and data frame communication with detectors placed at radiation zone. Reliability of CRC error detection capability alters with generator polynomial chosen. The most popular choice...
In this paper, we propose an architecture for Optimized Digital De-Skew Buffer (ODDB) with improved duty cycle correction using modified edge combiner and interpolator. The transmission gate based edge combiner suffers from the problem of glitches during the setup time and overshoots and undershoots afterwards. Our NAND gate based modified edge combiner, along with the interpolator, removes the glitches,...
This paper presents a 20-Gb/s half rate 4:1 multiplexer (MUX) with multiphase clock (MPC) architecture in 40-nm CMOS technology. The MPC architecture employs quarter-rate four-phase clock generated by true phase single clock divider, which omits the phase adjuster and delay-matching buffers and thus reduces power consumption. Meanwhile, The MUX is implemented by purely digital circuits contributing...
A gate-level simulator considering a multiple-event transient (MET) is proposed to design soft-error resilient VLSI chips for harsh radiation environments. Single event transients (SETs) at several logic gates might occur independently during a clock cycle, causing a wrong “pulse” captured in a D-flip-flop (D-F/F). To investigate the MET influence, SET effects at each gate are precisely modelled in...
Network-on-chip (NoC) has currently considered as a holistic solution over traditional and global bus-based system-on-chip (SoC) interconnections. However, NoC interconnects experience a subset of manufacturing faults- shorts, opens, and stuck-ats. A limitation of prior works on testing shorts on interconnects of a NoC is that interconnects are tested without coexistent open faults. The works then...
Time-to-Digital Converter (TDC) has been widely used in several applications such as time-of-flight measurement, high-energy physics experiment and bio-medical imaging. There are two generations of TDC implementation. In this paper we propose a SAR ADC design which has been adapted as a building block of the first generation of TDC. Design and simulation performed with 180nm CMOS technology, Our design...
With sonic technological developments, synthesizer has become a part of modern musical industries, one of which is the development of digital signal processing technology (DSP). In past few years, the trend to use sound synthesizer using mobile devices is continuing to increase. The main goal of mobile-based synthesizer is to achieve high quality audio and fast data processing speed with minimum power...
Nanosatellite has limited functions because of the mass constraint from 1 to 10 kg. Therefore, the requirement of low cost, low mass, low dimension, and low power consumption must be fulfilled in designing and choosing the component of nanosatellite. To obtain wider coverage area while maintaining the low dimension, camera array was used to produce image with wider area. In this research, On Board...
We introduce a fully integrated step-down self-oscillating switched-capacitor DC-DC converter that delivers near-threshold (NT) output voltages. The converter is built in 28 nm UTBB FD-SOI and occupies 0.0104 mm2. Back-gate biasing is utilized to increase the load power range. Measurements show a peak efficiency of 87%, self start-up capability, and a minimum efficiency of 75% for 79 nW to 200 μW...
A self-adjustable clock generator that closely tracks the voltage dependence of the critical path delay in a microprocessor is presented. Real-time frequency modulation performed by a tunable replica circuit (TRC) reduces the response time to a single cycle, by picking the appropriate phases of the delay-locked loop (DLL). The generator has wide tuning range of 550–2260 MHz at 1V supply voltage, works...
This paper proposes a fully-integrated high-conversion-ratio dual-output voltage boost converter (VBC) with maximum power point tracking (MPPT) circuits for low-voltage energy harvesting. The VBC consists of two voltage generators that generate Vout1 and VOUT2. Vout1 and VOUT2 are three and nine times higher than the harvester's output Vin, respectively. Vout1 is used as a supply voltage for on-chip...
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