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A new 1-bit full adder cell has been introduced in this paper. According to this approach body-biasing and semi domino logic both are used in a single full adder. Body-biasing technique is used to vary the threshold voltage to operate this adder at higher speed by allowing the faster gate switching. The important thing in this approach is that there is no requirement of any external circuitry for...
In this paper we present a highly-efficient 60V class-D power stage design in a 0.13μm SOI-based BCD process. The integrated output stage consists of a full H-bridge, level shifter, ramp generator, comparator, integrator, and preamplifier. Its performance was found to be better than previously published output stages implemented in SOI based BCD processes, which are typically more complex and costly...
Our goal is to create thin low-cost flexible NFC tags to allow everyday objects to communicate to smartphones and computers and thus participate in the Internet of Things. We employ amorphous Indium-Gallium-Zinc-Oxide (a-IGZO) thin-film transistor circuits processed at low temperatures, less than 250C, directly on thin polyester substrates. Reaching NFC standards with a-IGZO circuits is challenging...
Coverage is a major concern in simulation-based test and verification, but it usually addresses statements, conditions, or FSM transitions. The work reported here focuses on dynamic Assertion-Based Verification, which aims at checking that designs obey requirements formalized as temporal assertions. In that context, the selection of test sequences is related to coverage of the assertions activation...
SER is increasing for every IC process generation. Radiation induced soft errors are major concern in semiconductor memories due to technology scaling, higher integration densities and lower operating voltages. Nowadays memory cells are protected by using error correction codes. Among various multiple error correction codes ML decodable codes are suitable for memory applications due to their capability...
In this paper, design algorithms for implementing controllers for DC to AC converter and DC to DC converter using Field Programmable Gate Arrays (FPGA) are presented. We used DC to AC converter proposed in [1], which uses free oscillation and discrete energy injection technology for our experiments. For DC to DC converter, Cuk converter [2] was used in our experiments. The controller of DC to AC converter...
Multiplier is the most commonly used circuit in digital devices. Multiplication is one of the basic functions used in digital signal processing. Gate Diffusion Input (GDI) logic reduces the power dissipation and area of digital circuits while maintaining low complexity of logic design. In this paper, GDI technique is used for low-power design of 8-bit multiplier. Reduction in power and area can be...
This paper presents a temperature and supply compensated sub-threshold voltage reference generator which generates a reference voltage of 173 mV at supply voltage of 0.6 V and temperature @ 27 °C, has been designed in 45 nm CMOS technology. Variation of output voltage with temperature over a range of −25 to 85 °C is 172.88 to 173.25 mV which gives temperature coefficient of 19 ppm/°C at supply voltage...
Automatic test pattern generation for non-scan sequential circuits is an extremely challenging task. If successful, it can offer many benefits to the EDA community, ranging from manufacturing and functional test to post-silicon validation. High-level test generators often miss the low-level details, thus missing the detection of some gate-level faults. On the other hand, gate-level test generators...
Reversible logic synthesis has received considerable attention in the light of advances recently made in quantum computation. Implementation of a reversible circuit is envisaged by deploying several special types of quantum gates, such as k-CNOT. Although the classical stuck-at fault model is widely used for testing conventional CMOS circuits, new fault models, namely single missing-gate fault (SMGF),...
Communication in today's world is made efficient by digital data transmission. The digital communication employs parity generator at the source and parity checker at destination to ensure an error free transmission. This paper proposes the design of a 3-bit reversible even parity checker and generator using the basic reversible gates. The parity checker and generator circuit is designed using the...
We propose an Asynchronous-to-Synchronous Interface Controller (A2S-IC) with low delay-variation towards Process, Voltage and Temperature (PVT) variations for sub-threshold/near-threshold operation in low power applications. This A2S-IC is targeted for a full-range Dynamic Voltage Scaling (DVS) Global-Asynchronous-Local-Synchronous (GALS) Network-on-Chip (NoC). There are three key attributes in this...
A serial-input serial-output encoder based on pipelined rotate-left-accumulator (RLA) circuits is designed for multi-rate Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) codes of Chinese digital terrestrial/television multimedia broadcasting (DTMB) standard. The RLA circuit can make the area usage economical, and the pipelined architecture can simplify the memory structure. The encoder is implemented...
This paper presents a simple and robust control technique for distributed energy resources in microgrids. The technique utilizes the full potential of distributed energy resources, during grid connected and islanded operating modes. In grid-connected mode, the control pursues quasioptimum operation of the microgrid, so as to reduce distribution losses and voltage deviations while fully exploiting...
Using SiC MOSFET switches, this paper presents efficiency improvements in a dc-dc modular multilevel power electronic converter for wave energy extraction via electro active polymer. The total energy gain is estimated through a loss model for the SiC-MOSFET and compared with Si-IGBT based power electronic converter. Overall, in one energy cycle, up to 50% less energy loss was observed with the developed...
A change process in already deployed system requires its components to step through a few temporary states before they reach their desired states, however, most prevalent IT resource management tools seldom assume such temporary states. Therefore, the tools are not applicable to the change management of already deployed systems, particularly those that consist of hardware components. This paper addresses...
Synchronized detection is one of the major areas of photon counting applications, e.g., the quantum key distribution (QKD). With single photon avalanche diodes (SPADs), gated-mode operation has the advantage of reduced dark count probability thanks to the limited detection windows. On the other hand, passive quenching with active reset (PQAR) circuits can confine the afterpulsing probability with...
This paper briefly discusses the design of a low-cost, versatile and configurable error generator for PROFIBUS DP. Using a PROFICORE ULTRA oscilloscope trigger pulse, a small circuit designed around an Arduino MEGA 2560 disrupts messages on the industrial network, without adding an extra slave.
Simulation-based verification is still the most frequently used technique when complex designs are to be verified. Stimuli are thereby generated and applied in order to sufficiently trigger and, by this, verify a set of considered scenarios. In general, a scenario can be triggered in various fashions. To ensure a high verification quality, each of these fashions should adequately be covered. However,...
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