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In this paper we present a highly-efficient 60V class-D power stage design in a 0.13μm SOI-based BCD process. The integrated output stage consists of a full H-bridge, level shifter, ramp generator, comparator, integrator, and preamplifier. Its performance was found to be better than previously published output stages implemented in SOI based BCD processes, which are typically more complex and costly...
This paper presents A low noise, high PSRR low-dropout regulator for low-cost portable electronics. The proposed LDO uses an Operational Transconductance Amplifier (OTA) with Miller R-C compensation to ensure a stable phase margin greater than 62°. The active chip of the proposed regulator is only 150×680 um2. The design was simulated and lyouted in Cadence using mixed-signal 90 nm 2P9M CMOS process,...
This paper presents a design of a 5-bit 2Gsamples/s digital-to-analog converter (DAC) in 90-nm CMOS technology for DS-CDMA UWB transceivers applications. The proposed DAC was designed with a current binary weighted architecture for high frequency sampling rate. For low glitches, optimized deglitch circuit is adopted for the selection of current sources. The measured integral nonlinearity (INL) is...
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